CS250 DISCUSSION #2. Colin Schmidt 9/18/2014 Std. Cell Slides adapted from Ben Keller

Transcription

1 CS250 DISCUSSION #2 Colin Schmidt 9/18/2014 Std. Cell Slides adapted from Ben Keller

2 LAST TIME... Overview of course structure Class tools/unix basics

3 THIS TIME... Synthesis report overview for Lab 2 Lab 2 questions Lab 3 preview Deeper dive on standard cell libraries

4 LAB 1 METRICS About 75% of you reported time spent min: 5 hours; median: 10; mean: 12; max: 35 Base Lab Creating Struggling personal with accelerators base lab Hours Spent

5 LAB 2 All parts posted since Tuesday Most work for you: writing fast memory controller and using Jackhammer Most work for the tools: Synthesis Jobs Lab is due tomorrow at 9:30AM Questions after we talk about reports

6 SYNTHESIS REPORTS Using design compiler to synthesize your RTL to gates has multiple reports output QOR (quality of results) Timing Area Power Clock-gating Reference Resources

7 QOR General overview of the results Timing summaries Cell counts Areas Etc.

8 TIMING Shows multiple path groups we care about clk Detailed analysis of timing Top N critical paths Broken down by delay Goto for optimizing critical

9 AREA Breakdown of area per nameable unit Summary at top Combinational vs Noncombinational

10 POWER Operating point listed at top Power per module Dynamic (Switching + Internal) Static (Leak) Careful of units (defined at top)

11 CLOCK GATING Simple results of tools attempt to clock gate everything Does a very good job for our accelerator

12 REFERENCE Shows which standard cells were used in each module Well talk about how to read standard cell names and library name later toady

13 RESOURCES Synopsys provides implementations of many basic blocks (DesignWare) Shows which modules use these components, their parameters, and how the tools decided to optimize them (area, speed, etc)

14 LAB 2 QUESTIONS?

15 LAB 3: LESS RTL MORE TOOLS You ll be working with the tool flow Use SRAMs or Flops Use multiple Vt cells and different operating points Also using Jackhammer Try these as parameters Write scripts to find pareto optimal points Posted later this week - stay tuned

16 A STANDARD CELL LIBRARY ~cs250/manuals/saed...

17 A STANDARD CELL LIBRARY ~cs250/manuals/saed...

18 A STANDARD CELL LIBRARY ~cs250/manuals/saed...

19 A STANDARD CELL LIBRARY ~cs250/manuals/saed...

20 A STANDARD CELL

21 A STANDARD CELL Verilog files define functionality module NAND2X1_RVT (A1,A2,Y);! output Y;! input A1,A2;! nand #1 (Y,A2,A1);! `ifdef functional! `else! specify! specparam in1_lh_qn_hl=20,in1_hl_qn_lh=18,in2_lh_qn_hl=24,! in2_hl_qn_lh=22;! ( A1 -=> Y) = (in1_hl_qn_lh,in1_lh_qn_hl);! ( A2 -=> Y) = (in2_hl_qn_lh,in2_lh_qn_hl);! endspecify! `endif! endmodule

22 A STANDARD CELL.lib/.db files define timing and power timing () {! related_pin : "A1";! timing_sense : "negative_unate";! cell_rise ("del_1_7_7") {! index_1("0.016, 0.032, 0.064, 0.128, 0.256, 0.512, 1.024");! index_2("0.1, 0.25, 0.5, 1, 2, 4, 8");! values(" , , , , , , ", \! " , , , , , , ", \! " , , , , , , ", \! " , , , , , , ", \! " , , , , , , ", \! " , , , , , , ", \! " , , , , , , ");! }

23 A STANDARD CELL Y A1 A2 Y

24 A STANDARD CELL

25 WHAT ELSE MAKES A LIBRARY? Techfiles define process parameters (e.g., 1P9M)!!! TECHNOLOGY=saed32nm_1p9m_nominal! DIELECTRIC PASS1 { THICKNESS = 3.00 ER=3.9 }! CONDUCTOR MRDL { THICKNESS = 0.28 WMIN=2 SMIN=2 RPSQ=0.35 }! DIELECTRIC PASS2 { THICKNESS = 3.00 ER=3.9 }! CONDUCTOR M9 { THICKNESS = 0.19 WMIN=0.16 SMIN=0.16 RPSQ=0.28 }! DIELECTRIC D9 { THICKNESS = 0.6 ER=3.9 }! CONDUCTOR M8 { THICKNESS = WMIN=0.056 SMIN=0.056 RPSQ=0.1 }! DIELECTRIC D8 { THICKNESS = 0.6 ER=3.9 }

26 STANDARD CELL-BASED DESIGN IS GREAT! Area penalty for automation Dedicated teams of humans can probably still do better Much like compilers for code...

27 QUESTIONS?

28 BACKUPS

29 DIGITAL CIRCUIT TIMING Setup time?

30 DEFINITION: SETUP TIME tclk tclk-q + tpd + tsetup

31 DIGITAL CIRCUIT TIMING Hold time?

32 DEFINITION: HOLD TIME tcd + tclk-q thold

33 TIMING PROBLEM #1 70ps tclk-q = 30 ps 70ps 60ps 80ps 120ps tsetup = 50 ps 60ps 100ps thold = 0 ps 20ps 40ps 1. What is the minimum clock period of this circuit? 2. What is the fastest path through the circuit? Will this path violate the hold time?

34 TIMING SEEMS EASY! 70ps 70ps 60ps 80ps tclk = 410 ps 120ps 60ps 100ps 20ps 40ps thold < 90 ps Why is this a hard problem?

35 TIMING WOES, PART 1 Uniform delay of gates is a nice abstraction, but... Different rising vs. falling delays Some inputs faster than others Process variation Local changes in temperature Need more complicated (statistical) timing models

36 TIMING WOES, PART 2 Instantaneous clock propagation is a nice abstraction, but... Clock takes time to propagate across chip Clock skew; clock arrives at registers at different times

37 TIMING WOES, PART 3 Furthermore, many random sources of error cause jitter

38 TIMING WOES, PART 4 Verilog Source (Behav) Verilog Source (RTL) Constraints Std. Cell Library VCS VCS Design Compiler Behav Sim RTL Sim Guidance File Gate Level Netlist Delay File Constraints File Timing Area Execute SIM Execute SIM VPD Test Outputs VPD Test Outputs Formality Verification Results Design Vision GUI TLU+ Files IC Compiler (DP) Floor Plan Iterative design process DVE GUI DVE GUI VCS IC Compiler (P&R) Post Syn Sim Delay File Gate Level Netlist Constraints File Timing Area Layout Parasitics File Hard to make sure timing issues stay fixed Execute SIM VPD DVE GUI Test Outputs VCS Post P&R Sim Execute SIM IC Compiler GUI VPD Test Outputs DVE GUI VPD2VCD VCD PrimeTime Power Estimates

39 TIMING WOES, PART 5 tclk tclk-q + tpd + tsetup How to fix setup time violations? Increase the clock period! tcd + tclk-q thold How to fix hold time violations? You are screwed.

40 TIMING PROBLEM #2 70ps tclk-q = 30 ps 70ps 60ps tsetup = 50 ps 80ps 120ps thold = 0 ps 60ps 100ps tskew = +40 ps 20ps 40ps tjitter = ±30 ps Each gate propagates at ±10ps. What s the clock period? Any hold time violations?

41 FIXING SETUP TIME VIOLATIONS Speed up the critical path, not the whole circuit! Local fixes improve the whole chip

42 Logic optimization SETUP TIME FIXES

43 SETUP TIME FIXES Gate resizing - logical effort

44 SETUP TIME FIXES Register retiming (good for datapaths)

45 Intentional skew SETUP TIME FIXES

46 SETUP TIME FIXES If all else fails, just slow down the clock!

47 HOLD TIME FIXES Insert buffers on short paths Why not just add lots of buffers everywhere?

48 HOLD TIME FIXES Simulate across different process corners Generate ECO fixes at the very end of the design Margin for clock uncertainty (skew, jitter) Cross your fingers...

49 TIMING SUMMARY Meeting timing is one of the hardest parts of modern digital design Catching hold times can be tricky Failure to do so can be a showstopper! The tools are good, but a human touch helps