Synthesis. Other key files. Standard cell (NAND, NOR, Flip-Flop, etc.) FPGA CLB
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1 SYNTHESIS
2 Synthesis Involves synthesizing a gate netlist from verilog source code We use Design Compiler (DC) by Synopsys which is the most popular synthesis tool used in industry Target library examples: Standard cell (NAND, NOR, Flip-Flop, etc.) FPGA CLB Other key files source verilog (or VHDL) compile script output gate netlist many reports *.v (verilog) Synopsys Design Compiler.synopsys_dc.setup *.vg (gates) reports dc_compile std. cell library B. Baas 235
3 Standard Cell Library We currently use the 45 nm NanGate FreePDF45 Open Cell Library which is an open-source library developed by NanGate Inc, It contains 62 different functions ranging from buffers to scan flipflops with set and reset, including specialized low power cells with multiple drive strength variants, the library includes over 170 different standard cells. *.v (verilog) Synopsys Design Compiler.synopsys_dc.setup *.vg (gates) reports dc_compile std. cell library B. Baas 236
4 Compile Optimization Parameters There are many many configuration parameters which can be tuned to optimize the result of synthesis For homework/projects in this class, do not change any of these optimization parameters since this is not the focus of the class Only parameters to select input files should be changed Please talk to me if you would like to modify the script more extensively *.v (verilog) Synopsys Design Compiler *.vg (gates).synopsys_dc.setup reports dc_compile std. cell library B. Baas 237
5 Synthesis Key Files Makefile Contains all commands needed for simulation and synthesis Requires you to enter the top-level design name at the top of the file Type "make <return>" to see make targets and instructions dc-template.tcl Template used to generate a customized command file for Design Compiler Do not edit this file unless you are told you need to.synopsys_dc.setup Do not edit this file unless you are told you need to. Watch out for it since it appears in linux only with ls a and not just ls abc.v Very simple example design with 2-bit and 32-bit adders, and registers abc.vfv File that contains all source verilog files for simulation (NCVerilog or Verilog-XL) abc.vfs File that contains all source verilog files for synthesis (Design Compiler) B. Baas 238
6 Makefile rattle_179> make Make targets. Either change module name in Makefile or add the text 'NAME=xyz' after 'make' make print this help summary make clean deletes some generated files make cleanall deletes all generated files Make targets for simulation make compile compile only with.vfv and Verilog-XL make compilenc compile only with.vfv and NCVerilog make run run with NCVerilog make runxl run with Verilog-XL make viewer start simvision Make targets for synthesis make check compile only with.vfs and Verilog-XL make checknc compile only with.vfs and NCVerilog make synth synthesize default module Procedure to synthesize top-level module 'xyz' 1) change 'NAME := abc' to 'NAME := xyz' at top of Makefile 2) add all modules to be synthesized to file xyz.vfs 3) 'make check' and fix any errors 4) 'make synth' Alternate procedure: 1) add all modules to be synthesized to file xyz.vfs 2) 'make NAME=xyz check' and fix any errors 3) 'make NAME=xyz synth' B. Baas 239
7 Synthesis Timing clock ± 50 ps Example circuit where inputs and outputs are not registered so timing is extra complex abc.tim Startpoint: in0[0] (input port clocked by clk) Endpoint: out[0] (output port clocked by clk) Path Group: clk Path Type: max 4000 ps OR 750 ps synthesized logic clock edge n clock edge n+1 (@ 100 MHz) Point Incr Path clock clk (rise edge) clock network delay (ideal) input external delay f in0[0] (in) f U10/op (or2_2) f out[0] (out) f data arrival time clock clk (rise edge) clock network delay (ideal) clock uncertainty output external delay data required time data required time data arrival time slack (MET) Even thought the circuit does not contain registers (grayed out), the input and output signals are still timed with respect to them as if they were there. Timing is more straightforward when there are registers in the circuit. B. Baas 240
8 Synthesis Timing Estimated achievable cycle time = Target cycle time Timing slack A positive slack value implies that the circuit is estimated to perform at a higher clock rate than the target clock rate (1/TargetCycleTime) A negative slack value implies that the circuit is estimated to be unable to achieve the target clock frequency B. Baas 241
9 Synthesis Circuit Area abc.area **************************************** Report : area Design : abc Version: V SP2 Date : Thu Feb 3 15:56: **************************************** Library(s) Used: vtvtlib25 (File: /afs/ece/classes/html/winter04/eec281/lib/vtvtlib25.db) Number of ports: 31 Number of nets: 30 Number of cells: 10 Number of references: 1 Combinational area: Noncombinational area: Net Interconnect area: undefined (No wire load specified) Total cell area: Total area: undefined B. Baas 242
10 Synthesis Gate Netlist abc.vg module prac ( in0, in1, out, clk ); input [9:0] in0; input [9:0] in1; output [9:0] out; input clk; or2_2 U1 (.ip1(in0[9]),.ip2(in1[9]),.op(out[9]) ); or2_2 U2 (.ip1(in0[8]),.ip2(in1[8]),.op(out[8]) ); or2_2 U3 (.ip1(in0[7]),.ip2(in1[7]),.op(out[7]) ); or2_2 U4 (.ip1(in0[6]),.ip2(in1[6]),.op(out[6]) ); or2_2 U5 (.ip1(in0[5]),.ip2(in1[5]),.op(out[5]) ); or2_2 U6 (.ip1(in0[4]),.ip2(in1[4]),.op(out[4]) ); or2_2 U7 (.ip1(in0[3]),.ip2(in1[3]),.op(out[3]) ); or2_2 U8 (.ip1(in0[2]),.ip2(in1[2]),.op(out[2]) ); or2_2 U9 (.ip1(in0[1]),.ip2(in1[1]),.op(out[1]) ); or2_2 U10 (.ip1(in0[0]),.ip2(in1[0]),.op(out[0]) ); endmodule B. Baas 243
11 Synthesis, Other Output Files abc.cell All cells used Area per cell abc.logs General log file for synthesis Skip reading it for errors and warnings at your peril! abc.logv General log file for simulations Skip reading it for errors and warnings at your peril! B. Baas 244
12 Reported Circuit Power Don t trust power numbers Don t trust any uncalibrated CAD tool anyway Power comparisons are likely useful to estimate the value or cost of design modifications, however The greatest sources of inaccuracies come from: Interconnect (wires) dissipates a majority of the power in almost any design in a modern CMOS technology The synthesis tool may or may not even have an equation to estimate wire capacitance (and by E = CV 2, a way to estimate energy per operation) Even if it tries to estimate wire capacitance, it will surely be wrong! The only way to know it accurately is to do the actual cell placement and wire routing ("place & route") of the design B. Baas 245
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