3D2 Project Documentation MC68008 Microprocessor System. Mikhail Volkov, Niall Murphy, Wang Yunfeng Trinity College Dublin

Transcription

1 3D2 Project Documentation MC68008 Microprocessor System Mikhail Volkov, Niall Murphy, Wang Yunfeng Trinity College Dublin May 08,

2 Contents Part 1 Project Overview and Block Diagram Part 2 Detailed Project Schematics 2.1 Complete Project Schematic 2.2 GAL Pin Diagrams Part 3 Design and Implementation 3.1 Reset Circuitry 3.2 Bus Arbitration, Processor Status and Interrupt Control 3.3 Device Access and Memory Decoding 3.4 EPROM 3.5 RAM 3.6 Read-Modify-Write Cycle and Data Transfer Acknowledgement 3.7 Bus Error Eception 3.8 ACIA 3.9 Control LED 3.10 LED Array 3.11 Hacking the Monitor Part 4 Source Code 4.1 GAL A PALASM 4.2 GAL B PALASM 4.3 GAL C PALASM 4.4 Board Test 4.5 Control LED Test 4.6 LED Array Marquee 4.7 ACIA Test 2

3 The aim of the project is to design, construct and commission a simple MC68008 microprocessor system. The hardware comprises a MC68008 microprocessor, 8K EPROM, 4K RAM, 2 serial interfaces and relevant glue logic. Part 1- Project Overview and Block Diagram A block diagram of the project is shown below (Fig. 1.1). The diagram outlines in the most general sense, key dependencies between the components on the board. It should be noted that this is a purely functional diagram, not necessarily indicative of the actual wiring scheme implemented on the physical project board. For brevity, glue logic herein simply represents some form of interaction between two components, most likely arbitrated by programmable logic components, but possibly a direct connection. Fig. 1.1 Project Block Diagram 3

4 Part 3 Design and Implementation 3.1 Reset Circuitry The reset circuitry was required so that a button could be placed on the board to reset the system. This was especially useful in the initial debugging phase where we used the reset button in combination with the logic analyser to see what the processor was doing during start-up. The aim of the reset circuitry was simple: to provide an on-board button which would drive the reset and halt pins on the MC68008 low when pressed. This simple problem did however provide scope for some interesting design. The main difficulty with the reset circuitry is providing a smooth unambiguous signal, especially when the button is transitioning between its two positions. This is achieved using two Schmitt triggers. The Schmitt trigger is designed to give a high output when the input is above a certain value and a low output when the input is below a certain value. When the input is in between these thresholds, the output will retain its current value. This ensures that the reset signal will not jump back and forth between the high and low states when the button is pressed or released. Fig. 3.1 below provides a layout of the components involved in the reset circuitry. Fig. 3.1 Reset Circuitry 4

5 3.2 Bus Arbitration, Processor Status and Interrupt Control Bus arbitration control bus request and bus grant lines. The bus request (/BR) input enables eternal devices (such as a DMA or I/O controller) to gain access to the MC68008 bus. The CPU would give up the bus when it has completed its current bus cycle. The bus grant (/BG) output indicates that the MC68008 will release the bus at the end of the current bus cycle, resulting in the address bus, data bus, /AS, R/W, FC0, FC1 & FC2 being tri-stated and the CPU eecution being suspended. Fig. 3.2 below broadly illustrates the bus arbitration cycle in a fully functional MC68008 system. Fig. 3.2 Bus Arbitration Cycle Processor status is controlled by the function code lines FC0 FC2. These indicate the type of bus cycle currently being eecuted. Function code signals are valid when /AS is asserted. Interrupt control is provided by interrupt priority levels encoded on interrupt priority lines /IPL0 /IPL2. /IPL0 and /IPL2 are connected together, while /IPL1 remains on a separate line, thus limiting the number of interrupt levels to four: 000, 010, 101 and 111. Interrupt level 000 indicates that no interrupts are pending. Implementation of bus arbitration, processor status lines and interrupts was beyond the scope or timeframe of this project, although potential etensibility of these features was provided for. /BR was tied high to ensure that bus would not be requested. /BG and the interrupt lines were left floating. The GAL was programmed so that /VPA is asserted in the event of FC0, FC1 FC2 and /AS all being asserted. This allows the ACIAs to be etended with interrupt-driven functionality. 5

6 3.3 Device Access and Memory Decoding From the point of view of a programmer operating a complete and functional MC68008 microprocessor system, all memory accesses are encapsulated within a 1MB address space. That is to say the programmer can only refer to numerical memory locations, and has no direct control over individual devices. At the heart of this principle is the memory map, a routing scheme which maps values on the address lines into access requests to individual devices. The memory map is implemented by decoding an address and enabling the appropriate device. All devices must be assigned to unique addresses in the MC68008 memory space and two devices are never selected by the same address. Furthermore, the EPROM has to be located at address $00000 in order for the MC68008 to locate the initial system stack pointer (SSP) and program counter (PC), and to initialize the interrupt vector table. With these being the only requirements of the memory map, further considerations were given only towards simplification of logic and convenience of implementation. The memory map was implemented as follows: $00000 $01FFF: EPROM $02000: CTRL LED $08000: LED ARRAY $10000 $107FF: RAM0 $10800 $10FFF: RAM1 $F0000 $F07FF: ACIA0 $F0800 $F0FFF: ACIA1 Resolving the addressed into pins on the address lines results in the following access table: A19 A16 A15 A13 A11 A ENABLED DEVICE EEPROM 1 1 CTRL LED LED ARRAY RAM0 RAM ACIA0 ACIA1 Only five address pins are actually decoded. Access to devices is thus determined on a principle of elimination, rather than confirmation. That is to say, the address is not decoded fully, but only insofar as to disable all but one device. There is no danger in the event of an invalid address being provided. An invalid address simply means that no device will be enabled and DTACK will remain disasserted. 6

7 The resulting PALASM equations are as follows: /EPROM = /AS * /A19 * /A16 * /A13 /RAM0 = /AS * /A19 * A16 * /A11 /RAM1 = /AS * /A19 * A16 * A11 /ACIA0 = /AS * A19 * /A11 /ACIA1 = /AS * A19 * A11 The control LED and LED array require additional clauses, not related to memory decoding but rather to their specific modes of operation. These equations are eplained in detail in sections 3.6 and 3.7 of the report. 3.4 EPROM The EPROM module used in the project is a TMM2764AD 8192-byte 28-pin chip. The device is erased by eposing it to UV light for minutes and programmed electrically by changing bits from 1 to 0. The device provides 13 address lines and 8 data lines. The EPROM is enabled by asserting the chip enable (CE) pin low. /CE is asserted by the memory decoder provided /AS is asserted and the memory address on the address lines maps onto the EPROM memory space. Output is obtained by asserting the output enable (OE) pin low. /OE is asserted provided /DS is asserted and R/W is asserted (since the microprocessor is in read mode). 3.5 RAM There are two RAM modules used in the project, mapped to contiguous memory addresses between $10000 and $10FFF. The RAM modules are Hitachi HM6116P 2048-byte 24-pin chips. The device provides 11 address lines and 8 data lines. A RAM module is enabled by asserting the chip select (CS) pin low. /CS is asserted by the memory decoder provided /AS is asserted and the memory address on the address lines maps onto RAM memory space. Output is obtained by eactly the same logic as for the EPROM. /OE is asserted provided /DS is asserted and R/W is asserted (since the microprocessor is in read mode). Unlike the EPROM, the RAM can also be written to by the CPU. Data is written to the RAM by asserting the write enable (WE) pin low. /WE is asserted provided /DS is asserted and R/W is disasserted (since the microprocessor is in write mode). 7

8 3.6 Read-Modify-Write Cycle and Data Transfer Acknowledgement The read/write cycle of the MC68008 is outlined as follows. The MC68008 uses a single data strobe (/DS) and a read/write direction line R/W. In write mode, the CPU asserts R/W low, places appropriate values on the address and data lines, and after some setup time asserts /DS. The recipient device (memory or I/O controller) latches the data which is guaranteed to be valid before the leading edge of /DS and acknowledges by asserting /DTACK. The CPU completes the cycle by asserting DS and then (allowing for some hold time, in the event that the recipient is using transparent latches) disasserting the address and data lines. Thus the data is guaranteed to be valid while /DS is asserted. In read mode, the same mechanism applies with the difference being that the CPU holds the R/W line high (indicating a read cycle). The data source must provide valid data before /DS is disasserted. The access time involved in asserting /AS, decoding the memory address, accessing memory and setting up the data totals 212.5ns. Thus if the memory access time is 212.5ns, /DTACK can be generated directly from the memory decoder. The EPROM chip used in the project specifies a memory access time of 350ns, thus requiring 4 wait states before /DTACK can be asserted. For RAM access, no wait states are required and /DTACK is generated directly from the /RAM select signal in the memory decoder. Similarly the memory mapped LED array required no wait states as the device is driven directly by the memory decoder lines. Thus /DTACK is asserted whenever any device is enabled with the eception of EPROM which requires a delay of 4 wait states. The resulting PALASM equation is: /DTACK = (/EPROM * EPROM_ACTIVE) + /RAM0 + /RAM1 + LED_ACCESS The generation of the 4 required wait states for /DTACK is achieved through the emulation of a shift register such as a 74LS164. A shift register operates on the principle of advancing the value in each output to the net register on each rising edge of the clock signal. With AS acting as the clearing input to the shift register the resulting logic is such that once /AS is asserted the shift register will assert EPROM_ACTIVE 4 CPU clock cycles later. /DS is not necessary to include in the delay logic for the EPROM since the EPROM is a read-only device. The required layout is shown below (Fig. 3.3). The operation of the 74LS164 was emulated on the GAL. The resulting PALASM equations are provided below. LSB is an input pin tied to V CC and BSC_3 is the output pin providing EPROM_ACTIVE for the memory decoder. BSC_0 := LSB * /AS BSC_1 := BSC_0 * /AS BSC_2 := BSC_1 * /AS BSC_3 := BSC_2 * /AS 8

9 Fig. 3.3 Delayed /DTACK 9

10 3.7 Bus Error Eception In the event of neither /DTACK (in the case of memory devices) or /VPA (in the case of ACIA devices) not being asserted, an infinite wait state is prevented by asserting the bus error pin (BERR) low. /BERR is asserted if /AS remains asserted for too long (a nominal time period of 16μs was chosen as this corresponds to 128 CPU clock cycles). Two chained 74LS393 binary counters were chosen for this purpose. /AS acts as the clearing input (CLR) into both counters so that while AS is high the counters will remain clear, and as soon as /AS is asserted the counters least significant counter begins to increment. The most significant output digit of the two counters represents BERR so that if /AS is still asserted after 128 consecutive CPU clock cycles, this pin will be driven high. The signal is then put through a 74LS04 inverter and a SN7407 buffer, thus driving the output low and asserting the /BERR input pin of the CPU. A schematic illustrating the logic is show below (Fig. 3.4). Fig. 3.4 Bus Error Eception 10

11 3.8 ACIA The purpose of the ACIA is to provide an interface for the MC68008 to communicate with peripheral devices over a serial connection. In serial communication, data is transmitted sequentially, one bit at a time. The CPU data bus is a parallel connection with eight lines, wherein one byte of data is transmitted at a time. The ACIA is used as an interface between the parallel and serial connections. The ACIA contains a number of 8-bit registers which provide an interface to the MC68008 for transmitting and receiving data. These registers are as follows: Status Register: The status register is used to indicate transmission errors (framing and parity errors), overrun (where data is received before the processor has read previous data), status of transmit and receive registers (full or empty) and interrupt occurrences. Control Register: The control register is set by the programmer during ACIA initialisation. It is used to set the baud rate, the receiver clock source (eternal clock or baud rate), the word length and the number of stop bits. Command Register: The command register is also set by the programmer during initialisation. It is used to set the parity and interrupt modes. Transmitter Register: The programmer writes data here and it is automatically serialised and transmitted by the ACIA. Receiver Register: When the ACIA receives a serial signal it decodes it and places it in the Receiver Register where it can be read by the programmer. The ACIA operates using the E output of the MC68008 which is a special clock signal which is low for si CPU clock cycles and high for four. The ACIA uses the low part of this cycle to read the address lines and the read-write signal and the high part of the cycle to place the appropriate data on the data bus. The CPU reads the data on the end of the cycle (the downward edge of E). The ACIA requires a full cycle of E to function correctly and therefore, when a memory access involving the ACIA begins, we must wait for the start of an E cycle (begins on downward edge of E) before beginning the operation described above. We were able to implement this behaviour using two JK flip-flops. The first flip flop latches on a downward edge of E. If an ACIA memory access occurs, VPA will only be asserted at the point where E goes low. The second flip flop will assert VMA one clock cycle later. This activates the ACIA which will then check the states of the address lines (RS0 and RS1) and RW and either read from the data bus or place data on the data bus. This gives the ACIA a full cycle of E to perform a read or write. The reset pin of the ACIA is connected directly to the reset pin of the MC This means that the ACIA will be automatically reset when the CPU is reset. The ACIA has two pins which it uses to connect to a peripheral device, transmit data (TD) and receive data (RD). However, MOS technology uses 0V to represent '0' and 5V to represent '1' whereas the EIA RS232-C interface which we will be using to connect to the PC uses -25V...-3V to represent '1' and +3V...+25V to represent '0'. 11

12 A MAX232 chip is used for this purpose. The MAX232 will convert our 0V and 5V signals to +9V and -9V signals respectively. Conversely, when we receive data, we pass it through the MAX232 to convert the -12V and +12V signals to 5V and 0V signals respectively. The receiver input and transmitter output of the MAX232 were connected to a pin DIN socket. With the ACIA wired up, all that is left is to provide an interface to the programmer. A memory mapping technique was used to provide an intuitive procedure for communicating with the ACIA. The data registers for the first ACIA could be accessed by reading or writing from $F0000. The status register can be read from $F0001, and the command and control registers can be written to at $F0002 and $F0003 respectively. These equations were used in a GAL 22V10 to decode the address being accessed: /ACIA0 = /AS * A19 * /A11 /ACIA1 = /AS * A19 * A11 Before the ACIA can be used, it must be set to the appropriate mode of operation. This can be done by running an initialisation program. For this project, it was necessary to set the baud rate, set the parity mode and disable interrupts. This could be achieved using these lines of code: move.b #$0B,A0CR ;set command register move.b #$18,A0CTRL ;set control register The command register was set to ' '. This disabled transmitter interrupts, receiver interrupts and parity mode. The control register was set to ' '. This set the baud rate to 1200, the word length to 8 bits, the number of stop bits to 1 and selected the baud rate as the receiver clock source. Once initialised, two subroutines were needed for the programmer: one to read and one to write (see code listing 4.7). RACIA is used to read from the ACIA. It loops until bit 3 of the status register has been set (this will be set when the ACIA receives data) and then copies the receiver register into d0. WACIA is used to write to the ACIA. It loops until bit 4 of the status register has been set (this will be set when the transmitter register is empty) and then copies the least significant byte of d0 into the transmitter register. 12

13 3.9 Control LED A control LED is built into the project board allowing one to program simple glue logic to make the LED reflect arbitrary characteristics of the microprocessor system during operation. The LED was chosen to function as a read-write indicator. This is achieved by mapping it to a discrete memory address ($02000 was chosen, as outlined in section 3.3 on memory decoding) and providing logic to light the LED when R/W is asserted low during a memory access to this address, and turn off the LED when R/W is asserted high during a memory access to this address. In other words, writing $02000 lights the LED and reading from $02000 turns off the LED. This logic is implemented inside the GAL. Furthermore, the GAL output pin is latched onto itself such that it remains in its current state until the state of R/W changes. This means that writing to the control LED memory location will light the LED and keep it lit until the location is read from, and vice versa. This is achieved through the use of a self-referential holding equation in PALASM. The final PALASM equations implementing the control LED are as follows: STRING LED_SET '(/AS * /RW * A13)' LED_RESET = (/AS * RW * A13) LED = LED_SET + LED*/LED_RESET The use of address line A13 corresponds to memory location $ An intermediate LED_RESET output pin was required, rather than a string macro due to PALASM complications with parsing comple Boolean epressions. The following MC68008 program illustrates how the control LED is used. Successful eecution of this program results in the control LED flashing on and off at one-second intervals, thus (to an etent) verifying the correctness of the memory decoder, the readwrite cycle and the control LED implementation itself. LED equ $02000 DELAY equ org $0 dc.l $40800 dc.l main org $400 main move.b d0,led ; turn on LED move.l #DELAY,d1 ; initialise DELAY counter loop1 subq.l #1,d1 ; decrement bne loop1 ; loop until DELAY over move.b LED,d0 ; turn off LED move.l #DELAY,d1 ; initialise DELAY counter loop2 subq.l #1,d1 ; decrement bne loop2 ; loop until DELAY over bra main ; start again end 13

14 3.10 LED Array The LED array (also known as EPIC LED XTRAVAGANZA 9000!) is an etra project feature implemented by our group. The idea was to epand on the control LED principle, this time providing not one but four LEDs which can be independently turned on and off. Moreover, the intention was to provide an intuitive and easy to use interface for the programmer to write imaginative code which manipulates the LED array in different ways. We approached this task in a top down manner designing the code interface first, and the hardware second. The memory address representing the LED array was chosen to be $8000, as no other device in the memory space uses address line A15 so decoding would require only one pin to be checked. The main requirement of the interface specification was that a programmer could write a 4-bit value to the memory location mapped to the LED array, whereby each bit would represent a single LED in the array 1 to turn the LED on and 0 to turn it off. For eample, the following code would turn on LEDs 1 and 3: LEDARR EQU $8000 move.b #%0101,LEDARR This certainly felt more intuitive than using read and write instructions to toggle the LED on and off. It also allowed the programmer to user bitwise operations to create pretty light patterns. For instance, the following code would cause the lights to ignite in turn, creating a hypnotic scrolling LED marquee. This works by constantly rotating the value % and writing it to the LED array memory address, effectively equivalent to constantly shifting a one through an array of zeros. This was tested and found to captivate and entrance onlookers, causing them to stare at this dreamy light show for hours on end, sometimes slipping in and out of transient, hypnagogic states of consciousness. LEDARR EQU $8000 move.b #% ,d0 move.l #DELAY,d1 loop subq.l #1,d1 bne loop move.b d0,ledarr rol.b #1,d0 move.l #DELAY,d1 bra loop The entire functionality of the LED array was implemented on a single GAL, using 8 input pins, 4 intermediate pins and 4 output pins. The operation of the GAL is such that if /AS, /DS and /RW are asserted then LED will assume the value on input line D. The LED array GAL layout is shown in Fig The final implementation PALASM equations are as follows: 14

15 L0 = /AS * /DS * /RW * A15 * D0 + L0 * /L0_RESET L0_RESET = /AS * /DS * /RW * A15 * /D0 L1 = /AS * /DS * /RW * A15 * D1 + L1 * /L1_RESET L1_RESET = /AS * /DS * /RW * A15 * /D1 L2 = /AS * /DS * /RW * A15 * D2 + L2 * /L2_RESET L2_RESET = /AS * /DS * /RW * A15 * /D2 L3 = /AS * /DS * /RW * A15 * D3 + L3 * /L3_RESET L3_RESET = /AS * /DS * /RW * A15 * /D3 Fig. 3.5 LED Array Implementation 15

16 3.11 Hacking the Monitor The final challenge we set ourselves for this project was to hack the monitor program and inject our own subroutine which would provide an end-user HyperTerminal interface for toggling the LEDs on and off. Success in this task would be a final indication that every component of the board is working perfectly, and would surely be a final testament to our efforts and our understanding of the underlying hardware and software involved in the design and implementation of our microprocessor system. The task was to introduce an additional entry into the monitor main menu and to allow the user to enter our subroutine by pressing the M key. Therein by pressing the number keys 1 4 the user should be interactively able to toggle the corresponding LEDs on our project board. In addition, the HyperTerminal display should update to reflect the current state of the LED array. Finally, by pressing any other key the user would be brought back to the main menu and the monitor would resume normal functionality. It was also essential that whatever changes we introduce should not interfere with the monitor s eisting mode of operation. The monitor program is a robust and sophisticated piece of software, totalling just over 1000 lines of assembly code. To hack the monitor we first had to figure out eactly how it worked. The monitor initializes by clearing the vector table and installing default eception handlers. Net the monitor initializes the ACIAs, since without properly functioning ACIAs the program would not be able to communicate with HyperTerminal and appear dead to the end-user. The ACIA baud rate is initialized by polling for an input character and comparing it to equivalent characters at different baud rates. After initializing the ACIA baud rate and some further data structure initialization, the monitor enters the command interpreter polling loop. Here the monitor polls for key presses and upon receiving a key compares it to entries in a command table. The command table is a lookup table consisting of an ASCII value representing a key-press, a menu entry message and an address for the appropriate subroutine. This was our first point of modification. We added a custom entry for our subroutine onto the end of the command table and proceeded to eplore further. DC.B 0 COMTAB DC.W (' '),SPMSG,SPACE DC.W ('G'),GMSG,G DC.W ('H'),HMSG,H DC.W ('L'),LMSG,L DC.W $0C,CLMSG,CL DC.W ('O'),OMSG,O DC.W ('R'),RMSG,R DC.W ('S'),SMSG,S DC.W ('Z'),ZMSG,Z dc.w ('M'),MMSG,M ; our new entry COMEND 16

17 The menu entry messages are all defined in one place at the bottom of the end of the monitor program. We added our own: MMSG dc.b 'EPIC LED XTRAVAGANZA 9000!',CR,LF,0 The net step was to write and integrate our subroutine into the monitor. By pressing one of the keys numbered 1 4 the user would be presented with a line which looks like this: [.] [X] [.] [.] The contents of each pair of brackets represent the state of a given LED in the LED array. X means the LED is turned on (presumably the user has just pressed 2) and a dot means the LED is turned off. An empty template message (like the one above but with all dots) was added onto our message table: MMSG dc.b 'EPIC LED XTRAVAGANZA 9000!',CR,LF,0 MMSG0 dc.b '[.] [.] [.] [.]',CR,LF,0 The idea was to edit this message at runtime to reflect the state of the LEDs. However, since the program resides in the EPROM, and the EPROM is read-only, this would not be possible. So a decision was made to reserve a chunk of RAM space into which the readonly message could be copied at the start of our subroutine. The message could then be edited at runtime. So in addition to the memory-mapped address of our LED array was added another pre-processor directive specifying a location in memory where the LED display string could be copied to: LEDARR EQU $8000 LEDMEM EQU $10A00 Now finally we could write the subroutine itself. First the registers are backed up. Net the LED array is initialized by copying 0 into LEDARR. The LED display message is copied from the EPROM to RAM and its effective address is loaded into a0. The polling loop consists of reading in a character from the ACIA and comparing the value read in with ASCII characters 1 4. If a match is found then the bit location corresponding to the key press value minus one (bit locations 0 3) are tested to see if the bit is set. If the bit is set the LED is turned off, otherwise the LED is turned on, thus toggling the LED with successive key presses. The address in a0 is incremented by an appropriate byte-sized offset in order to align it with the correct place in the LED display message. Finally the new LED state is written to LEDARR and either an X or a dot is written to the address stored in a0. Control flow branches back to the start of the loop if a match was found; otherwise the registers are restored and the program returns from the subroutine. The final source code for the M subroutine is listed below. (Minor modifications such as a goodbye message and an added entry into the Help menu are omitted for brevity.) 17

18 ** ** EPIC LED XTRAVAGANZA 9000! ** ~~~~~~~~~~~~~~~~~~~~~~~~~~ ** M movem.l d0-d1/a0-a1,-(sp) move.b #0,d1 lea MMSG0,a0 lea LEDMEM,a1 MCPMSG move.b (a0)+,(a1)+ tst.b (a0) bne MCPMSG M0 move.b d1,ledarr lea LEDMEM,a0 CALL CALL WRSTR RACIA M1 cmp.b #'1',d0 bne M2 btst #0,d1 beq M1SET M1RST and.b #%1110,d1 adda #1,a0 move.b #'.',(a0) bra M0 M1SET or.b #%0001,d1 adda #1,a0 move.b #'X',(a0) bra M0 M2 cmp.b #'2',d0 bne M3 btst #1,d1 beq M2SET M2RST and.b #%1101,d1 adda #5,a0 move.b #'.',(a0) bra M0 M2SET or.b #%0010,d1 adda #5,a0 move.b #'X',(a0) bra M0 M3 cmp.b #'3',d0 bne M4 btst #2,d1 beq M3SET M3RST and.b #%1011,d1 adda #9,a0 move.b #'.',(a0) bra M0 M3SET or.b #%0100,d1 adda #9,a0 move.b #'X',(a0) bra M0 M4 cmp.b bne #'4',d0 MRTS btst beq #3,d1 M4SET 18

19 M4RST and.b #%0111,d1 adda #13,a0 move.b #'.',(a0) bra M0 M4SET or.b #%1000,d1 adda #13,a0 move.b #'X',(a0) bra M0 MRTS movem.l (sp)+,d0-d1/a0-a1 move.b #0,LEDARR rts PAGE 19

20 Part 4 Source Code 4.1 GAL A PALASM TITLE GALA PATTERN template.pds REVISION 3 AUTHOR COMPANY Mikhail Volkov, Niall Murphy, Wang Yunfeng Trinity College Dublin DATE CHIP GAL1 PAL22V10 ; ; PINS ; PIN 1 PIN 2 PIN 3 PIN 4 ;PIN 5 ;PIN 6 PIN 7 ;PIN 8 ;PIN 9 PIN 10 PIN 11 PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 PIN 20 PIN 21 PIN 22 PIN 23 CLK A11 EPROM_ACTIVE A13 A16 A19 RW AS ACIA0 ACIA1 RAM0 RAM1 EPROM DTACK ACIA_ACTIVE LED_RESET LED CLK2 ; ; STRINGS ; STRING LED_ACCESS STRING LED_SET '(/AS * A13)' '(/AS * /RW * A13)' ; EQUATIONS ; CLK2 := /CLK2 /EPROM = /AS * /A19 * /A16 * /A13 /RAM0 = /AS * /A19 * A16 * /A11 /RAM1 = /AS * /A19 * A16 * A11 /ACIA0 = /AS * A19 * /A11 /ACIA1 = /AS * A19 * A11 ACIA_ACTIVE = /ACIA0 + /ACIA1 /DTACK = (/EPROM * EPROM_ACTIVE) + /RAM0 + /RAM1 + LED_ACCESS LED_RESET = (/AS * RW * A13) LED = LED_SET + LED*/LED_RESET 20

21 4.2 GAL B PALASM TITLE GALB PATTERN template.pds REVISION 3 AUTHOR Mikhail Volkov, Niall Murphy, Wang Yunfeng COMPANY Trinity College Dublin DATE CHIP GAL1 PAL22V10 ; ; PINS ; PIN 1 PIN 2 PIN 3 PIN 4 PIN 5 ;PIN 6 PIN 7 PIN 8 PIN 9 ;PIN 10 ;PIN 11 ;PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 ;PIN 19 PIN 20 PIN 21 PIN 22 PIN 23 CLK2 AS DS RW LSB FC0 FC1 FC2 OE WE CLK8 CLK4 VPA BSC_0 BSC_1 BSC_2 BSC_3 ; EQUATIONS ; /OE = RW * /DS /WE = /RW * /DS BSC_0 := LSB * /AS BSC_1 := BSC_0 * /AS BSC_2 := BSC_1 * /AS BSC_3 := BSC_2 * /AS /VPA = FC0 * FC1 * FC2 * /AS CLK4 := /CLK4 CLK8 := /CLK8*CLK4 + CLK8*/CLK4 21

22 4.3 GAL C PALASM TITLE GALC PATTERN template.pds REVISION 1 AUTHOR Mikhail Volkov, Niall Murphy, Wang Yunfeng COMPANY Trinity College Dublin DATE CHIP GAL1 PAL22V10 ; ; PINS ; PIN 1 PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 ;PIN 10 ;PIN 11 ;PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 PIN 20 PIN 21 ;PIN 22 ;PIN 23 CLK AS DS RW A15 D0 D1 D2 D3 L0 L0_RESET L1 L1_RESET L2 L2_RESET L3 L3_RESET ; EQUATIONS ; L0 = /AS * /DS * /RW * A15 * D0 + L0 * /L0_RESET L0_RESET = /AS * /DS * /RW * A15 * /D0 L1 = /AS * /DS * /RW * A15 * D1 + L1 * /L1_RESET L1_RESET = /AS * /DS * /RW * A15 * /D1 L2 = /AS * /DS * /RW * A15 * D2 + L2 * /L2_RESET L2_RESET = /AS * /DS * /RW * A15 * /D2 L3 = /AS * /DS * /RW * A15 * D3 + L3 * /L3_RESET L3_RESET = /AS * /DS * /RW * A15 * /D3 22

23 4.4 Board Test org $0 dc.l $40800 dc.l main org $1000 main jmp main 4.5 Control LED Test LED equ $02000 DELAY equ org $0 dc.l $40800 dc.l main org $1000 main move.b d0,led ; turn on LED move.l #DELAY,d1 ; initialise DELAY counter loop1 subq.l #1,d1 ; decrement bne loop1 ; loop until DELAY over move.b LED,d0 ; turn off LED move.l #DELAY,d1 ; initialise DELAY counter loop2 subq.l #1,d1 ; decrement bne loop2 ; loop until DELAY over bra main ; start again end 4.6 LED Array Marquee LEDARR equ $8000 DELAY equ org dc.l $0 $40800 dc.l main org $1000 main move.b # ,d0 ; store marquee move.l #DELAY,d1 ; initialise DELAY counter loop subq.l #1,d1 ; decrement bne loop ; loop until DELAY over move.b d0,ledarr ; write marquee to LED array rol.b #1,d0 ; rotate marquee bra loop ; start again end 23

24 4.7 ACIA Test RAM EQU $10000 ; RAM RAMMAX EQU RAM+4096 ; 4K A0DAT EQU $F0000 ; ACIA0 data register A0ST EQU A0DAT+1 ; ACIA0 status register A0CR EQU A0DAT+2 ; ACIA0 command register A0CTRL EQU A0DAT+3 ; ACIA0 control register A1DAT EQU $F0800 ; ACIA1 data register A1ST EQU A1DAT+1 ; ACIA1 status register A1CR EQU A1DAT+2 ; ACIA1 command register A1CTRL EQU A1DAT+3 ; ACIA1 control register LED EQU $2000 ; LED memory map DELAY EQU ; 1 second delay ORG $0 DC.L DC.L RAMMAX INIT rmsg dc.b $0A,$0D,'Enter a character: ',0 wmsg dc.b $0A,$0D,'You have entered ',0 ORG $1000 INIT0 MOVE.L #40000,D0 IACIA0 DBEQ D0,IACIA0 MOVE.B D0,A0ST TST.B A0DAT MOVE.B #$0B,A0CR MOVE.B #$18,A0CTRL MOVE.L (SP)+,D0 START MOVE.B D0,LED move.b #% ,d2 move.b d2,$8000 loop0 lea rmsg,a0 loop1 move.b (a0)+,d0 bsr wacia tst.b d0 bne loop1 bsr racia move.b d0,d1 loop2 lea wmsg,a0 move.b (a0)+,d0 bsr wacia tst.b d0 bne loop2 move.b d1,d0 bsr wacia rol.b #1,d2 move.b d2,$8000 bra loop0 24

25 * subroutine to read a char from the ACIA * at eit: D0 = character [ASCII] RACIA BTST.B #3,A0ST ;loop until... BEQ.S RACIA ;ACIA ready MOVE.B A0DAT,D0 ;move char in ACIA to d0 ANDI.L #$7F,D0 ;clear parity bit RTS * subroutine to write a char to the ACIA * at entry: D0 = character to be written [ASCII] WACIA BTST.B #4,A0ST ;loop until... BEQ.S WACIA ;data register empty MOVE.B D0,A0DAT ;move char in D0 into the ACIA RTS 25