# BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

Size: px
Start display at page:

Download "BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book"

Transcription

1 BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book

2 Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write to a memory Homework assignments 2

3 Recall concept of a decoder Interpret as a function code decoder 3

4 In many digital systems it is required to connect multiple output devices onto the same wire or group of wires Output device: Switch (outputs a voltage, which indicates the state of the switch) Input device: LED (requires an applied voltage to turn the light on/off). Problem: What happens when two or more devices attempt to drive different voltages on the same wire (or group of wires, i.e., a bus) Result: line (or bus) contention, damage to circuit. 4

5 For example, consider two devices Device A and Device B need to send voltages to Device C What would happen if A sent +5 V and B sent V at the same time? Line contention: it s like Device A s positive terminal power supply is connected to ground. Not good! Common Ground 5V Device A Device B 5V Output Devices Voltage Source Device C Input Device Voltage Sink 5

6 A SOLUTION: TRI-STATE BUFFER 6

7 APPLICATION OF TRI-STATE BUFFER Write Control Device A Device B Active low tri-state buffer Device C Active high tri-state buffer Only one device can output a voltage (V or 5V) at one time. Therefore, the outputs of the Device A and B may be connected together, safely. 7

8 Number A Number B Carry In Sum Carry Out x _ y _ C in _ S _ C out _ Carry Axis x + y + C in Arithmetic Sum -bit Binary Number Wheel Add FULL ADDER Truth Table x y C in C out S Full Adder Block Diagram x y From a Karnaugh map: S = x y z + x y z + x y z + x y z Logical OR C out = x y + x z + yz C in S FA We taught (designed) the digital circuit how to add using the -bit number wheel. C out 8

9 Number A Number B Borrow In Difference Borrow Out x _ y _ B in _ D _ B out _ Carry (Borrow) Axis x - y - B in Arithmetic Difference -bit Binary Number Wheel Subtract Truth Table x y B in B out D From a Karnaugh map: D = S = x y z + x y z + x y z + x y z Logical OR B out = x y + x z + yz C out = x y + x z + yz Full Subtracter Block Diagram x y FS B in B out D We taught (designed) the digital circuit how to subtract using the -bit number wheel. 9

10 i Number A 3 2 A i Carry Axis Add 4-BIT Number B Carry In Sum B i C i S i -bit Binary Number Wheel FULL Carry Out C i+ B 3 A 3 B 2 A 2 B A B A ADDER C 4 FA S 3 C 3 FA S 2 C 2 FA S C FA S C May be extended to n-bit full adder and corresponding n-bit number wheel. Most Significant Carry Axis Add 4-bit Binary Number wheel

11 4-BIT AND and OR CIRCUITS A 3 A 3 F 3 F 3 B 3 B 3 A 2 A 2 F 2 F 2 B 2 B 2 A F A F B B A A F F B B Other functions such as XOR, NAND, NOR, and NOT may be similarly implemented.

12 4-BIT ARITHMETIC LOGIC UNIT (ALU) SIMPLIFIED FUNCTIONAL DESCRIPTION OUTPUTS C out F C B SWITCH (MUX) 4 FA 4 FS 4 AND 4 OR A B MS 3 S 2 S S C IN TWO 4-BIT NUMBERS FUNCTION SELECTOR INPUTS 2

13 EXAMPLE 4-BIT ALU FUNCTION TABLE S3 S2 S S LOGIC M= A A B B ARITHMETIC M= A AND B A PLUS B A OR B A MINUSB A NAND B A + A A - B B + A XOR B B - 3

14 OPTIMIZED VERSION R 3 R 2 R R ADDS TO OPERANDS WHEN ADD/SUB = C 3 CONTAINS 4-BIT FA AND LOGIC CIRCUITS AS ABOVE, BUT DOES NOT HAVE FS C A 3 A 2 A A MOST SIGNIFICANT CARRY OR BORROW B 3 B 2 B B PERFORMS S COMPLEMENT OF B WHEN ADD/SUB = A B = A + 2s(B) ADD/SUB CONTROL 4

15 In this course, we do not use the optimized, 2 s complement ALU. The optimized version does not contain a FS circuit. We use the non-optimized, basic ALU, which does contain a FS circuit. This means that in this course, the ALU has a FS circuit to perform subtraction. 5

16 There are three types of memories: Flip Flop (FF) (-bit storage) and Latch What is the difference between a Flip Flop and a Latch? Register (n-bit storage) Memory (m-words by n-bits of storage) 6

17 Word Word n- m x n Memory m = 2 k words Each word has n-bits Word 2 k - p- p-bit register Flip-flop (-bit) 7

18 MEMORY (SEQUENTIAL) CIRCUITS 8

19 WAYS TO TRIGGER A FLIP FLOP LATCH FLIP FLOP 9

20 REGISTER Can be designed as a group of flip flops Example: 4-bit register, or a 4-bit word 2

21 WRITING TO A REGISTER 2

22 WRITING TO A REGISTER Write Timing Diagram Data Input OE (optional) D 3 D 2 D D Valid CLK (external) CLK (internal) Q 3 Q 2 Q Q Q 3 =D 3,Q 2 =D 2,Q =D,Q =D Valid 22

23 READING FROM A REGISTER Read Timing Diagram OE Q 3 Q 2 Q Q O 3 O 2 O O Valid Note: other control designs are possible: For example, R/W and OE could be input to a 2-input AND gate, whose output could be connected to the Enable pins of the tri-state buffers. 23

24 MEMORY Example: 8 x 4 Memory Eight Words, and each word has 4-bits 8 x 4 Memory 8 = 2 3 words, and each word has 4-bits Address 3-bit Data 4-bit Words A A D D A 2 D 2 D 3 R/Wn OE CS Block Diagram Representation 24

25 m x n MEMORY m x n Memory m = 2 k words, and each word has n-bits A A A k-2 m by n Memory D D... D n- A k- OE CS 25

26 WRITING TO MEMORY 26

28 EXAMPLE: 4X3 MEMORY Example: 4 x 3 Memory Four Words, and each word has 3-bits 4 x 3 Memory 4 = 2 2 words, and each word has 3-bits Address 2-bit Data 3-bit Words A A D D D 2 R/Wn OE CS Block Diagram Representation 28

29 BLOCKING AND ENABLING PROPERTY OF AND GATE E X Y If E =, then Y = X (Enable) If E =, then Y = (Block) Example Application: Clock Enable E CLK Y If E =, then Y = If E =, then Y = 29

30 Schematic Block Diagram A A D D D 2 R/Wn OE CS Input data pins and output data pins are separated to simplify the analysis. 3

31 EXAMPLE Goal: Write b to location b, i.e., write 5 to location 2. End result should be: A A D D D 2 R/Wn OE CS 3

32 Step : Setup data word: b Data Address R/Wn CS At this point in time, the voltages (data) are applied to pins I 2 -I. = V = 5 V 32

33 Step : Setup data word: b Data Address R/Wn CS At this point in time, the voltages have flowed to the inputs of the FFs. = V = 5 V 33

34 Step : Setup data word: b Data Address R/Wn CS Also at this point in time, the V applied to pin CS has forced V at the CLK inputs of the FFs. = V = 5 V 34

35 Step : Setup data word: b Step 2: Setup address: b Data Address R/Wn CS At this point in time, the address applied to pins A -A has flowed to the Word Select gates. = V = 5 V 35

36 Step : Setup data word: b Step 2: Setup address: b Data Address R/Wn CS Due to {A A } = {}, Word 2 Select Line is the only active word select line. = V = 5 V 36

37 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Data Address R/Wn CS R/Wn is normally low (), so write mode is selected. = V = 5 V 37

38 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Step 4: Trigger the circuit by making CS= Data Address R/Wn CS At this point in time, the Write gate at Word 2 becomes. = V = 5 V 38

39 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Step 4: Trigger the circuit by making CS= Data Address R/Wn CS Also at this point in time, the CLK inputs to the FFs of Word 2 undergo a position transition. = V = 5 V 39

40 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Step 4: Trigger the circuit by making CS= Data Address R/Wn CS Also at this point in time, the data () is written into the FFs of Word 2. = V = 5 V 4

41 HOMEWORK: PERFORM A SIMILAR ANALYSIS FOR READ Show the incremental steps and timing diagram required to read the data located at memory location b. A A D D D 2 R/Wn OE CS 4

42 A BLANK MEMORY FOR YOU 42

43 HOMEWORK: PROBLEM STATEMENT Design a circuit that stores the 5-bit result of the last addition operation performed by a 4-bit full adder (FA) to an 8 words x 4-bit memory. Use an 8x4 memory that has similar control signals as the 4x3 memory given in the previous slides. Store the 5-bit result as follows: Step : store the MSb of the 5-bit result to Bit- of address of the memory. Ensure that the other bits of address are set to zero. Step 2: take the 4-bit output of the 4-bit FA circuit and store it at address of the memory. Use a given clock signal to execute the above steps and write to the memory. 43

44 HOMEWORK: PROBLEM STATEMENT PICTORIALLY CLK Given ALU C F3 F2 F F Your Circuit A A C F3F2FF Desired Result D D A 2 D 2 D 3 R/Wn OE CS 44

### REGISTER TRANSFER LANGUAGE

REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro

### ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks

ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class next-next Mon MLK Day ECE230 Review

### UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT

UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic

### Parallel logic circuits

Computer Mathematics Week 9 Parallel logic circuits College of Information cience and Engineering Ritsumeikan University last week the mathematics of logic circuits the foundation of all digital design

### EE 3170 Microcontroller Applications

EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline

### CHAPTER 4: Register Transfer Language and Microoperations

CS 224: Computer Organization S.KHABET CHAPTER 4: Register Transfer Language and Microoperations Outline Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations

### REGISTER TRANSFER AND MICROOPERATIONS

REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

### Let s put together a Manual Processor

Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

### Computer Architecture and Organization: L04: Micro-operations

Computer Architecture and Organization: L4: Micro-operations By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com, hafez@research.iiit.ac.in 1 Outlines 1. Arithmetic microoperation 2.

### END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

### EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS

EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,

### Chapter 4. The Processor

Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified

### DIGITAL ELECTRONICS. P41l 3 HOURS

UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Final Exam Solution Sunday, December 15, 10:05-12:05 PM

Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals

### REGISTER TRANSFER AND MICROOPERATIONS

1 REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

### LECTURE 4. Logic Design

LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two

### CMPE 413/ CMSC 711. Project Specification: 16 bit 2 s complement Adder and 8 bit 2 s complement multiplier. GND. Input bus. Latches I[8]-I[15]

Project Specification: 16 bit 2 s complement Adder and 8 bit 2 s complement multiplier. Assigned: Fri, Nov 3rd Due: Tue, Dec. 19th Description: con1 I[15] I[14] I[13] GND I[12] I[11] I[10] I[9] con2 O[15]

### COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital

Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in

### Question Total Possible Test Score Total 100

Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

### ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### For Example: P: LOAD 5 R0. The command given here is used to load a data 5 to the register R0.

Register Transfer Language Computers are the electronic devices which have several sets of digital hardware which are inter connected to exchange data. Digital hardware comprises of VLSI Chips which are

### COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic

### Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

### Dec Hex Bin ORG ; ZERO. Introduction To Computing

Dec Hex Bin 0 0 00000000 ORG ; ZERO Introduction To Computing OBJECTIVES this chapter enables the student to: Convert any number from base 2, base 10, or base 16 to any of the other two bases. Add and

### 6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate logical values from place to place.

### The functional block diagram of 8085A is shown in fig.4.1.

Lecture-13 Internal Architecture of Intel 05A The functional block diagram of 05A is shown in fig.4.1. INTA INTR RST7.5 RST5.5 RST6.5 TRAP SOD SID INTERRUPT SERIAL I/O (Internal Bus) FR(S) IR() B() C()

### Register Transfer and Micro-operations

Register Transfer Language Register Transfer Bus Memory Transfer Micro-operations Some Application of Logic Micro Operations Register Transfer and Micro-operations Learning Objectives After reading this

### Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

### QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

### R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

### ECE260: Fundamentals of Computer Engineering

Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction

### ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ELCT 501: Digital System Design

ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

### CHAPTER 5 : Introduction to Intel 8085 Microprocessor Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY

CHAPTER 5 : Introduction to Intel 8085 Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY The 8085A(commonly known as the 8085) : Was first introduced in March 1976 is an 8-bit microprocessor with 16-bit address

### Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations

Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations

### Combinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems.

REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

### CSE303 Logic Design II Laboratory 01

CSE303 Logic Design II Laboratory 01 # Student ID Student Name Grade (10) 1 Instructor signature 2 3 4 5 Delivery Date -1 / 15 - Experiment 01 (Half adder) Objectives In the first experiment, a half adder

### Chapter 4. The Processor

Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations

### 1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE:

1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE: A microprocessor is a programmable electronics chip that has computing and decision making capabilities similar to central processing unit

### Systems Programming. Lecture 2 Review of Computer Architecture I

Systems Programming www.atomicrhubarb.com/systems Lecture 2 Review of Computer Architecture I In The Book Patt & Patel Chapter 1,2,3 (review) Outline Binary Bit Numbering Logical operations 2's complement

### Lecture #21 March 31, 2004 Introduction to Gates and Circuits

Lecture #21 March 31, 2004 Introduction to Gates and Circuits To this point we have looked at computers strictly from the perspective of assembly language programming. While it is possible to go a great

### Contents. Chapter 9 Datapaths Page 1 of 28

Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for

### Digital Systems. John SUM Institute of Technology Management National Chung Hsing University Taichung, ROC. December 6, 2012

Digital Systems John SUM Institute of Technology Management National Chung Hsing University Taichung, ROC December 6, 2012 Contents 1 Logic Gates 3 1.1 Logic Gate............................. 3 1.2 Truth

### Combinational Logic Circuits

Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has

### Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

### CS222: Processor Design

CS222: Processor Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Processor Design building blocks Outline A simple implementation: Single Cycle Data pathandcontrol

### Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying

### Microcomputers. Outline. Number Systems and Digital Logic Review

Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded

### Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019

### Real Digital Problem Set #6

Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch

### 6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals

### Music. Numbers correspond to course weeks EULA ESE150 Spring click OK Based on slides DeHon 1. !

MIC Lecture #7 Digital Logic Music 1 Numbers correspond to course weeks sample EULA D/A 10101001101 click OK Based on slides 2009--2018 speaker MP Player / iphone / Droid DeHon 1 2 A/D domain conversion

### Lecture 21: Combinational Circuits. Integrated Circuits. Integrated Circuits, cont. Integrated Circuits Combinational Circuits

Lecture 21: Combinational Circuits Integrated Circuits Combinational Circuits Multiplexer Demultiplexer Decoder Adders ALU Integrated Circuits Circuits use modules that contain multiple gates packaged

### Digital Logic the Bare Minimum

Digital Logic the Bare Minimum Norman Matloff University of California at Davis updated October 31, 1999 Contents 1 Overview 2 2 Combinational Logic 2 2.1 A Few Basic Gates.......................................

### FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital

### Reference Sheet for C112 Hardware

Reference Sheet for C112 Hardware 1 Boolean Algebra, Gates and Circuits Autumn 2016 Basic Operators Precedence : (strongest),, + (weakest). AND A B R 0 0 0 0 1 0 1 0 0 1 1 1 OR + A B R 0 0 0 0 1 1 1 0

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Summer 2003 Lecture 21 07/15/03

Summer 2003 Lecture 21 07/15/03 Simple I/O Devices Simple i/o hardware generally refers to simple input or output ports. These devices generally accept external logic signals as input and allow the CPU

### Topics. Midterm Finish Chapter 7

Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory

### Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

### Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS

Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.

### Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when

### Combinational Logic II

Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

### UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

### Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register

### CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015

CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

### The Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined

### CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016

CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

### Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation

### LABORATORY MANUAL VLSI DESIGN LAB EE-330-F

LABORATORY MANUAL VLSI DESIGN LAB EE-330-F (VI th Semester) Prepared By: Vikrant Verma B. Tech. (ECE), M. Tech. (ECE) Department of Electrical & Electronics Engineering BRCM College of Engineering & Technology

### EE 109L Review. Name: Solutions

EE 9L Review Name: Solutions Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False:

### Digital Logic Design Exercises. Assignment 1

Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system

### Levels in Processor Design

Levels in Processor Design Circuit design Keywords: transistors, wires etc.results in gates, flip-flops etc. Logical design Putting gates (AND, NAND, ) and flip-flops together to build basic blocks such

### Arithmetic-logic units

Arithmetic-logic units An arithmetic-logic unit, or ALU, performs many different arithmetic and logic operations. The ALU is the heart of a processor you could say that everything else in the CPU is there

### 1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085.

(1) Draw and explain the internal architecture of 8085. The architecture of 8085 Microprocessor is shown in figure given below. The internal architecture of 8085 includes following section ALU-Arithmetic

### IA Digital Electronics - Supervision I

IA Digital Electronics - Supervision I Nandor Licker Due noon two days before the supervision 1 Overview The goal of this exercise is to design an 8-digit calculator capable of adding

### EKT 422/4 COMPUTER ARCHITECTURE. MINI PROJECT : Design of an Arithmetic Logic Unit

EKT 422/4 COMPUTER ARCHITECTURE MINI PROJECT : Design of an Arithmetic Logic Unit Objective Students will design and build a customized Arithmetic Logic Unit (ALU). It will perform 16 different operations

### Computer Organization (Autonomous)

Computer Organization (Autonomous) UNIT I Sections - A & D Prepared by Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. SYLLABUS Introduction: Types of Computers, Functional units of Basic Computer (Block

### A Simple Parallel Input Port

308 Apr. 8, 2002 A Simple Parallel Input Port We want a port which will read 8 bits of data from the outside Such a port is similar to or Port B when all pins are set up as input We need some hardware

### CSE140: Components and Design Techniques for Digital Systems

CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at

Ripple-Carry Adder Binary Adders x n y n x y x y c n FA c n - c 2 FA c FA c s n MSB position Longest delay (Critical-path delay): d c(n) = n d carry = 2n gate delays d s(n-) = (n-) d carry +d sum = 2n

### CS 261 Fall Mike Lam, Professor. Combinational Circuits

CS 261 Fall 2017 Mike Lam, Professor Combinational Circuits The final frontier Java programs running on Java VM C programs compiled on Linux Assembly / machine code on CPU + memory??? Switches and electric

### Logic design Ibn Al Haitham collage /Computer science Eng. Sameer

DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as

### University of Toronto Mississauga. Flip to the back cover and write down your name and student number.

University of Toronto Mississauga Midterm Test Course: CSC258H5 Winter 2016 Instructor: Larry Zhang Duration: 50 minutes Aids allowed: None Last Name: Given Name: Flip to the back cover and write down

### Midterm Project Design of 4 Bit ALU Fall 2001

Midterm Project Design of 4 Bit ALU Fall 2001 By K.Narayanan George Washington University E.C.E Department K.Narayanan Fall 2001 1 Midterm Project... 1 Design of 4 Bit ALU... 1 Abstract... 3 1.2 Specification:...

### Chapter 4 Arithmetic Functions

Logic and Computer Design Fundamentals Chapter 4 Arithmetic Functions Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Iterative combinational

### In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.

1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.

### Chapter 4. The Processor Designing the datapath

Chapter 4 The Processor Designing the datapath Introduction CPU performance determined by Instruction Count Clock Cycles per Instruction (CPI) and Cycle time Determined by Instruction Set Architecure (ISA)

### Chapter 4. Combinational Logic. Dr. Abu-Arqoub

Chapter 4 Combinational Logic Introduction N Input Variables Combinational Logic Circuit M Output Variables 2 Design Procedure The problem is stated 2 The number of available input variables & required

### EECS Components and Design Techniques for Digital Systems. Lec 20 RTL Design Optimization 11/6/2007

EECS 5 - Components and Design Techniques for Digital Systems Lec 2 RTL Design Optimization /6/27 Shauki Elassaad Electrical Engineering and Computer Sciences University of California, Berkeley Slides

### HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

### DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

### Lecture 10: Combinational Circuits

Computer Architecture Lecture : Combinational Circuits Previous two lectures.! TOY machine. Net two lectures.! Digital circuits. George Boole (85 864) Claude Shannon (96 2) Culminating lecture.! Putting

### EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN

11-1 EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN Purpose Extend the design of the basic four bit adder to include other arithmetic and logic functions. References Wakerly: Section 5.1 Materials Required

EE 352 Unit 8 HW Constructs Logic Circuits Combinational logic Perform a specific function (mapping of 2 n input combinations to desired output combinations) No internal state or feedback Given a set of