BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book


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1 BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book
2 Decoder Tristate device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write to a memory Homework assignments 2
3 Recall concept of a decoder Interpret as a function code decoder 3
4 In many digital systems it is required to connect multiple output devices onto the same wire or group of wires Output device: Switch (outputs a voltage, which indicates the state of the switch) Input device: LED (requires an applied voltage to turn the light on/off). Problem: What happens when two or more devices attempt to drive different voltages on the same wire (or group of wires, i.e., a bus) Result: line (or bus) contention, damage to circuit. 4
5 For example, consider two devices Device A and Device B need to send voltages to Device C What would happen if A sent +5 V and B sent V at the same time? Line contention: it s like Device A s positive terminal power supply is connected to ground. Not good! Common Ground 5V Device A Device B 5V Output Devices Voltage Source Device C Input Device Voltage Sink 5
6 A SOLUTION: TRISTATE BUFFER 6
7 APPLICATION OF TRISTATE BUFFER Write Control Device A Device B Active low tristate buffer Device C Active high tristate buffer Only one device can output a voltage (V or 5V) at one time. Therefore, the outputs of the Device A and B may be connected together, safely. 7
8 Number A Number B Carry In Sum Carry Out x _ y _ C in _ S _ C out _ Carry Axis x + y + C in Arithmetic Sum bit Binary Number Wheel Add FULL ADDER Truth Table x y C in C out S Full Adder Block Diagram x y From a Karnaugh map: S = x y z + x y z + x y z + x y z Logical OR C out = x y + x z + yz C in S FA We taught (designed) the digital circuit how to add using the bit number wheel. C out 8
9 Number A Number B Borrow In Difference Borrow Out x _ y _ B in _ D _ B out _ Carry (Borrow) Axis x  y  B in Arithmetic Difference bit Binary Number Wheel Subtract Truth Table x y B in B out D From a Karnaugh map: D = S = x y z + x y z + x y z + x y z Logical OR B out = x y + x z + yz C out = x y + x z + yz Full Subtracter Block Diagram x y FS B in B out D We taught (designed) the digital circuit how to subtract using the bit number wheel. 9
10 i Number A 3 2 A i Carry Axis Add 4BIT Number B Carry In Sum B i C i S i bit Binary Number Wheel FULL Carry Out C i+ B 3 A 3 B 2 A 2 B A B A ADDER C 4 FA S 3 C 3 FA S 2 C 2 FA S C FA S C May be extended to nbit full adder and corresponding nbit number wheel. Most Significant Carry Axis Add 4bit Binary Number wheel
11 4BIT AND and OR CIRCUITS A 3 A 3 F 3 F 3 B 3 B 3 A 2 A 2 F 2 F 2 B 2 B 2 A F A F B B A A F F B B Other functions such as XOR, NAND, NOR, and NOT may be similarly implemented.
12 4BIT ARITHMETIC LOGIC UNIT (ALU) SIMPLIFIED FUNCTIONAL DESCRIPTION OUTPUTS C out F C B SWITCH (MUX) 4 FA 4 FS 4 AND 4 OR A B MS 3 S 2 S S C IN TWO 4BIT NUMBERS FUNCTION SELECTOR INPUTS 2
13 EXAMPLE 4BIT ALU FUNCTION TABLE S3 S2 S S LOGIC M= A A B B ARITHMETIC M= A AND B A PLUS B A OR B A MINUSB A NAND B A + A A  B B + A XOR B B  3
14 OPTIMIZED VERSION R 3 R 2 R R ADDS TO OPERANDS WHEN ADD/SUB = C 3 CONTAINS 4BIT FA AND LOGIC CIRCUITS AS ABOVE, BUT DOES NOT HAVE FS C A 3 A 2 A A MOST SIGNIFICANT CARRY OR BORROW B 3 B 2 B B PERFORMS S COMPLEMENT OF B WHEN ADD/SUB = A B = A + 2s(B) ADD/SUB CONTROL 4
15 In this course, we do not use the optimized, 2 s complement ALU. The optimized version does not contain a FS circuit. We use the nonoptimized, basic ALU, which does contain a FS circuit. This means that in this course, the ALU has a FS circuit to perform subtraction. 5
16 There are three types of memories: Flip Flop (FF) (bit storage) and Latch What is the difference between a Flip Flop and a Latch? Register (nbit storage) Memory (mwords by nbits of storage) 6
17 Word Word n m x n Memory m = 2 k words Each word has nbits Word 2 k  p pbit register Flipflop (bit) 7
18 MEMORY (SEQUENTIAL) CIRCUITS 8
19 WAYS TO TRIGGER A FLIP FLOP LATCH FLIP FLOP 9
20 REGISTER Can be designed as a group of flip flops Example: 4bit register, or a 4bit word 2
21 WRITING TO A REGISTER 2
22 WRITING TO A REGISTER Write Timing Diagram Data Input OE (optional) D 3 D 2 D D Valid CLK (external) CLK (internal) Q 3 Q 2 Q Q Q 3 =D 3,Q 2 =D 2,Q =D,Q =D Valid 22
23 READING FROM A REGISTER Read Timing Diagram OE Q 3 Q 2 Q Q O 3 O 2 O O Valid Note: other control designs are possible: For example, R/W and OE could be input to a 2input AND gate, whose output could be connected to the Enable pins of the tristate buffers. 23
24 MEMORY Example: 8 x 4 Memory Eight Words, and each word has 4bits 8 x 4 Memory 8 = 2 3 words, and each word has 4bits Address 3bit Data 4bit Words A A D D A 2 D 2 D 3 R/Wn OE CS Block Diagram Representation 24
25 m x n MEMORY m x n Memory m = 2 k words, and each word has nbits A A A k2 m by n Memory D D... D n A k OE CS 25
26 WRITING TO MEMORY 26
27 READING FROM MEMORY 27
28 EXAMPLE: 4X3 MEMORY Example: 4 x 3 Memory Four Words, and each word has 3bits 4 x 3 Memory 4 = 2 2 words, and each word has 3bits Address 2bit Data 3bit Words A A D D D 2 R/Wn OE CS Block Diagram Representation 28
29 BLOCKING AND ENABLING PROPERTY OF AND GATE E X Y If E =, then Y = X (Enable) If E =, then Y = (Block) Example Application: Clock Enable E CLK Y If E =, then Y = If E =, then Y = 29
30 Schematic Block Diagram A A D D D 2 R/Wn OE CS Input data pins and output data pins are separated to simplify the analysis. 3
31 EXAMPLE Goal: Write b to location b, i.e., write 5 to location 2. End result should be: A A D D D 2 R/Wn OE CS 3
32 Step : Setup data word: b Data Address R/Wn CS At this point in time, the voltages (data) are applied to pins I 2 I. = V = 5 V 32
33 Step : Setup data word: b Data Address R/Wn CS At this point in time, the voltages have flowed to the inputs of the FFs. = V = 5 V 33
34 Step : Setup data word: b Data Address R/Wn CS Also at this point in time, the V applied to pin CS has forced V at the CLK inputs of the FFs. = V = 5 V 34
35 Step : Setup data word: b Step 2: Setup address: b Data Address R/Wn CS At this point in time, the address applied to pins A A has flowed to the Word Select gates. = V = 5 V 35
36 Step : Setup data word: b Step 2: Setup address: b Data Address R/Wn CS Due to {A A } = {}, Word 2 Select Line is the only active word select line. = V = 5 V 36
37 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Data Address R/Wn CS R/Wn is normally low (), so write mode is selected. = V = 5 V 37
38 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Step 4: Trigger the circuit by making CS= Data Address R/Wn CS At this point in time, the Write gate at Word 2 becomes. = V = 5 V 38
39 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Step 4: Trigger the circuit by making CS= Data Address R/Wn CS Also at this point in time, the CLK inputs to the FFs of Word 2 undergo a position transition. = V = 5 V 39
40 Step : Setup data word: b Step 2: Setup address: b Step 3: Select write mode Step 4: Trigger the circuit by making CS= Data Address R/Wn CS Also at this point in time, the data () is written into the FFs of Word 2. = V = 5 V 4
41 HOMEWORK: PERFORM A SIMILAR ANALYSIS FOR READ Show the incremental steps and timing diagram required to read the data located at memory location b. A A D D D 2 R/Wn OE CS 4
42 A BLANK MEMORY FOR YOU 42
43 HOMEWORK: PROBLEM STATEMENT Design a circuit that stores the 5bit result of the last addition operation performed by a 4bit full adder (FA) to an 8 words x 4bit memory. Use an 8x4 memory that has similar control signals as the 4x3 memory given in the previous slides. Store the 5bit result as follows: Step : store the MSb of the 5bit result to Bit of address of the memory. Ensure that the other bits of address are set to zero. Step 2: take the 4bit output of the 4bit FA circuit and store it at address of the memory. Use a given clock signal to execute the above steps and write to the memory. 43
44 HOMEWORK: PROBLEM STATEMENT PICTORIALLY CLK Given ALU C F3 F2 F F Your Circuit A A C F3F2FF Desired Result D D A 2 D 2 D 3 R/Wn OE CS 44
45 HOMEWORK: YOUR SOLUTION 45
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