Central Processing Unit. Steven R. Bagley

Size: px

Start display at page:

Download "Central Processing Unit. Steven R. Bagley"

Kathleen Waters
5 years ago
Views:

1 Central Processing Unit Steven R. Bagley

2 Introduction So far looked at the technology underpinning computers Logic signals to cause things to happen, and represent numbers Boolean gates to combine and manipulate those signals Flip-Flops/RAM to store things

3 The CPU Central Processing Unit the brain of the computer Constructed out of logic gates and flip-flops Talks to the rest of the system by sending logic signals on its various pins except the CPU is very dumb

4 68000 This is the processor by Motorola, a typical 16-bit CPU from the 1980s. The pinout is typical of most CPUs, although things aren t as straightforward now

5 68000 This is the processor by Motorola, a typical 16-bit CPU from the 1980s. The pinout is typical of most CPUs, although things aren t as straightforward now

68000 V CC (2) GND(2) CLK ADDRESS BUS A23 A1 DATA BUS D15 D0 AS PROCESSOR STATUS FC0 FC1 FC2 R/W UDS LDS DTACK ASYNCHRONOUS BUS CONTROL MC6800 PERIPHERAL CONTROL E VMA VPA BR BG BGACK BUS ARBITRATION

6 68000 V CC (2) GND(2) CLK ADDRESS BUS A23 A1 DATA BUS D15 D0 AS PROCESSOR STATUS FC0 FC1 FC2 R/W UDS LDS DTACK ASYNCHRONOUS BUS CONTROL MC6800 PERIPHERAL CONTROL E VMA VPA BR BG BGACK BUS ARBITRATION CONTROL SYSTEM CONTROL BERR RESET HALT IPL0 IPL1 IPL2 INTERRUPT CONTROL This is the processor by Motorola, a typical 16-bit CPU from the 1980s. The pinout is typical of most CPUs, although things aren t as straightforward now

7 CPU-System Communication Main signals used to communicate with the system are: Address Bus Data Bus Read/Write Easier to understand if we consider how they are used

8 Memory Memory is just a collection of flip-flops Usually arranged into groups that can be addressed individually Often multiples of eight (i.e.bytes) By an address, just a binary number Not just RAM

9 Example Memory Map FF8000 I/O Space FA0000 Cartridge ROM F00000 Hard Drive ROM E FFFFF RAM 8 0 ROM From Atari STe not to scale! Also ROM, and lots of computers use what s called Memory-mapped IO. Hardware devices appear as if they were parts of the computer s memory

10 PHoto of 16 ram chips, one for each word in the ATARI st

11 PHoto of 16 ram chips, one for each word in the ATARI st

12 Writing to Memory CPU puts the address of where to store data on the Address Bus CPU sets the read/write signal to write CPU puts the data it wants to store on the Data Bus System decodes address and stores data CPU waits for the transaction to complete How transaction finishing is done depends on the CPU with the 68000, there s a Data Transfer ACKnowledge signal (DTACK)

13 Reading from Memory CPU sets the read/write signal to read CPU puts the address of where of data to be read from on Address Bus System decodes address and places data on Data bus CPU waits for the transaction to complete and then reads data from Data bus

14 System System needs to decode the address And route the data signals to/from the right place Done using standard boolean logic Bits from the address lines combined to form chip select signals for the relevant parts of the system System often designed to make it easy to decode Saw this last week with the ST hard drive interface

15 Example of the ATARI ST Book s IDE hard drive circuit

16 Work out what is happening at each gate connected to the input Then combine those gates

17 Work out what is happening at each gate connected to the input Then combine those gates

18 Build up on paper the logic equations for the various points A

19 A B Build up on paper the logic equations for the various points

20 A B C Build up on paper the logic equations for the various points

21 A IDECS B C Build up on paper the logic equations for the various points

22 A IDECS B C Build up on paper the logic equations for the various points

23 A IDECS B C Build up on paper the logic equations for the various points

24 A IDECS B C IDECS0 Build up on paper the logic equations for the various points

25 A IDECS B C IDECS1 IDECS0 Build up on paper the logic equations for the various points

26 CPU But how does the CPU know what to do? It executes a sequence of instructions Each instruction tells the CPU to do one thing But where does it get these instructions from?

27 CPU Instructions CPU gets instructions from the computer s memory Each instruction is encoded as a binary pattern (an opcode) Each CPU family has its own Instruction Set Which are usually incompatible with other CPU families

28 4 different CPUs instruction to increment a register. Although in most cases not the only way you can do it. I m not even going to attempt to work out what the value would be on the x86 probably around 0x40

29 68000 ADDQ #1, D0 0x different CPUs instruction to increment a register. Although in most cases not the only way you can do it. I m not even going to attempt to work out what the value would be on the x86 probably around 0x40

30 68000 ARM ADDQ #1, D0 ADD R0, R0, #1 0x5280 0xE different CPUs instruction to increment a register. Although in most cases not the only way you can do it. I m not even going to attempt to work out what the value would be on the x86 probably around 0x40

31 68000 ARM 6502 ADDQ #1, D0 ADD R0, R0, #1 ADC #1 0x5280 0xE x69 0x01 4 different CPUs instruction to increment a register. Although in most cases not the only way you can do it. I m not even going to attempt to work out what the value would be on the x86 probably around 0x40

32 68000 ARM 6502 x86 ADDQ #1, D0 ADD R0, R0, #1 ADC #1 INC %eax 0x5280 0xE x69 0x01 4 different CPUs instruction to increment a register. Although in most cases not the only way you can do it. I m not even going to attempt to work out what the value would be on the x86 probably around 0x40

33 CPU Instructions Opcode size varies with different Instruction Sets ARM ISA has opcodes that are exactly 32-bits wide x86 has a variable instruction width (1 to 16 bytes) Fixed instruction width makes it much easier to build a CPU x86 doesn t know how long the instruction is until it starts decoding it

34 Von Neumann Architecture Memory shared between program and data In a von Neumann machine, there s no difference between memory containing data and program Although data usually doesn t make sense as a program Named after John von Neumann ( ) who came up with the idea Although it does in some cases

35 Von Neumann Architecture The von Neumann architecture has a single address space Some addresses contain program opcodes Others contain data If you write data to an address containing program, you change the program Named after John von Neumann ( )

36 Harvard Architecture Not the only approach Harvard architecture has separate memory spaces for program and data So storing data at an address won t affect program memory (which it would in the von Neumann model) Modern CPUs are a hybrid of Harvard and von Neumann architecture

37 Harvard Architecture Harvard architecture has two address spaces One contains program, the other data Accessed separately by the CPU Named after John von Neumann ( )

38 0xFFFF Program and Data Program Data 0x0000 von Neumann Harvard

39 Modern CPUs Ostensibly use a von Neumann architecture But the implementations (to make them fast) give them Harvard-like Unless you are writing specialised forms of code (self-modifying/self-generating code) then they can be thought of as von Neumann

40 Fetch - Decode - Execute CPU sits in a cycle of: Fetching an instruction Decoding the instruction Executing it Which may involve accessing memory again Next instruction then fetched

Chapter Operation Pinout Operation 35

Chapter Operation Pinout Operation 35 68000 Operation 35 Chapter 6 68000 Operation 6-1. 68000 Pinout We will do no construction in this chapter; instead, we will take a detailed look at the individual pins of the 68000 and what they do. Fig.