System-Level ASIC Algorithm Simulation Platform using Simulink

Transcription

1 Security Level: System-Level ASIC Algorithm Simulation Platform using Simulink Dr. Sun, Defu Huawei Technologies Co., LTD. 2015/11/03

2 Contents p Background p System- Level Algorithm Simulation Tool Options p Challenges and Solutions in System- Level Simulation p Future Work Page 2

3 Background Huawei Technologies Co., LTD. Global leading supplier of information and communication solutions. Dedicated to Telecom operators, Enterprise and Consumer industries to provide competitive and comprehensive solutions and services. So far, Huawei s products and solutions are in more than 170 countries and regions, serving more than 1/3 of the world s population. l Employees 170K, R&D: 70K+, 150 countries all around the world l 15 business units, service in 170+ countries and regions l Patents: l Participation in Standards and Open Source Organizations: 170+ (180+ Positions) l Revenue in 2014 $46B,2015 H1 $28B,YoY Growth 30%

4 Background Presenter n Dr. Sun, Defu, USTC, Ph.D. of Communication and Information. n System Engineer in Huawei Technologies Co., LTD. Major focus on Physical Layer algorithm research including Wireless LTE, Microwave, Copper DSL/Cable algorithms and architectures. Dr. Sun has 7-year experience in baseband and intermediate frequency physical layer algorithms.

5 Algorithm Simulation/Verification Workflow in ASIC Floating Point Design/Verification Fixed Point Design/Verification Floating/Fixed Point Comparison Algorithm/ASIC Comparison Sub-module Simulation Sub-module Fixed Point Design/Verification Sub-module Floating/Fixed Point Comparison Module Level Comparison Link-Level Simulation/Verification Link-Level Fixed Point Optimization/ Verification Link-Level Floating/Fixed Point Comparison Link-Level Comparison Floating Point Performance OK Fixed Point Performance OK Comparison OK Characteristics of ASIC Algorithm Simulation/Verification 1. System Level Design and Verification of Floating Point Arithmetic 2. Accurate Fixed Point design and Performance Comparison with Floating Point 3. Performance Comparison between Fixed Point Algorithm and RTL in ASIC Compared to conventional floating point algorithm simulation, for ASIC algorithm verification is more extensive to verify accuracy with high degree of confidence

6 Algorithm ASIC Algorithm Simulation Platform Requirements u Modular Simulation and Visualization.Algorithm structure corresponds to the chip architecture. AAF Synchroniz ation CH EST EQ DMAP DFEC Simulation Workflow ASIC Design Workflow Model Based Design:Clear algorithm architecture;matching algorithm structure and ASIC architecture;easy comparison between algorithm simulation and chip performance

7 ASIC Algorithm Simulation Platform Requirements u Easy Transformation of Algorithm Timing and Control TX RX Bit Clock Bit Clock Algorithm Module 1 Symbol Clock Symbol Clock Sub-module1 (System Clock) Sub-module 2 Symbol Clock TX System Clock RX System Clock Multiple Clocks in different algorithms Single algorithm module may needs multiple clocks ASIC algorithm simulation involves symbol and system clocks, as well as other clock conversions. Simulation platform must provide convenient clocking scheme.

8 ASIC Algorithm Simulation Platform Requirements u Algorithm simulation can simulate the real ASIC performance Algorithm Simulation Synchroniz ation CH EST EQ DMAP DFEC ASIC Algorithm Simulation Synchroniz ation Time delay CH EST Time delay EQ Time delay DMAP Time delay DFEC p Time- Delay Algorithms:Loop Filter, FEC, software processing p Time- Sensitive Algorithms:Phase- noise compensation, Algorithmic phase- jumps ASIC algorithm simulation needs to consider the impact of processing delays in ASIC

9 ASIC Algorithm Simulation Platform Requirements u Easy performance comparison between algorithm simulation and ASIC Sub-Module Comparison Fixed point input Algorithm Module System Comparison Bit Comparison output Level-Level Comparison ASIC Module 1-1 matching between algorithm and ASIC module; Easy switch between modules and system/link level

10 ASIC Algorithm Simulation Platform Requirements u Other Requirements p Comprehensive Toolbox p Accurate Location of Bugs and Easy Debugging p High Simulation Efficiency

11 ASIC Algorithm Simulation Platform Requirements Visual & Modular Simple Timing Conversion Real ASIC Performance Simple Performance Comparison Comprehensive Toolbox Debugging and Localization Efficient Simulation MathWorks MATLAB & Simulink is great for algorithm simulation in ASIC Huawei consider it as important ASIC algorithm verification tool Page 11

12 Challenge and Solutions u Efficient ASIC algorithm simulation p ASIC algorithms require execution of a large number of simulations for verification. The efficiency of simulation is critical, and a big challenge p Through fully automated pipelined and parallel simulation, to maximize simulation efficiency. p Manually configure simulation parameters, and simulate p Manually configure module, organize data and document p Manually configure Simulink to generate C (Simulink Coder), configure data comparison, organize data and document p Automatic parameterization and simulation with script p Automatically generate C from Simulink, script parameters, RM files/code, and generate simulation figures/tables/documents p Automated comparison of data at any level of modules/system p Efficient Pipeline Simulation approaches Manual Simulink Simulation Semi-Automatic Simulink to C Automatic Simulink Simulation Phase Ⅰ Phase Ⅱ Phase Ⅲ

13 Challenge and Solutions u High efficiency ASIC algorithm simulation and verification p Partition into sub- modules, increase pipelining. Higher performance but more resources. p Due to synchronization of the data, maximum latency of the modules is the bottleneck, leading to compromise of efficiency. No. Serial Simulation Time Module Module Module Module Example of simulation efficiency improvement Pipelined Parallel Simulation Time / Simulation Time Reduction Total %

14 Challenge and Solutions u Off- line ASIC Algorithm Simulation and Verification p It is crucial for ASIC algorithm performance verification to integrate real channel models p Co- Simulation between Simulink and channel model simulators improve algorithm s robustness Tx Simulink Verification Platform Channel Models Rx Simulink Verification Platforms Tx Simulink Verification Platform Data Acquis ition Off-line Simulation Platform Data Acquis ition Rx Simulink Verification Platforms Performance Output p For ultra high- speed signal processing (e.g. WDM transmission), the symbol rate could be >10Gs/s, where FPGA cannot support verification, so off- line verification is the most effective method.

15 Future Work u Make full use of existing tools to improve the efficiency of fixed- point algorithm development p Consider using Fixed- Point Designer and automated tools to improve efficiency of conversion and reduce the risk of human error. u Improve simulation efficiency for large numbers of simulations p Further improve efficiency for a single simulation run p Consider and validate parallel simulations, and leverage computing capability of multi- core computers / clusters. u Improve off- line simulation capability p Enhance verification through using prototype hardware with test equipment Page 15

16 Thank you