CISC 360 Midterm Exam - Review Alignment

Transcription

1 CISC 360 Midterm Exam - Review Alignment Michela Taufer October 14, 2008 Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective, R. Bryant and D. O'Hallaron, Prentice Hall, CS:APP 2003

2 Alignment Aligned Data Primitive data type requires K bytes Address must be multiple of K Required on some machines; advised on IA32 treated differently by Linux and Windows! Motivation for Aligning Data Memory accessed by (aligned) double or quad-words Inefficient to load or store datum that spans quad word boundaries Virtual memory very tricky when datum spans 2 pages Compiler Inserts gaps in structure to ensure correct alignment of fields 2 CISCʼFa08

3 Specific Cases of Alignment Size of Primitive Data Type: 1 byte (e.g., char) no restrictions on address 2 bytes (e.g., short) lowest 1 bit of address must be bytes (e.g., int, float, char *, etc.) lowest 2 bits of address must be bytes (e.g., double) Windows (and most other OSʼs & instruction sets):» lowest 3 bits of address must be Linux:» lowest 2 bits of address must be 00 2» i.e., treated the same as a 4-byte primitive data type 12 bytes (long double) Linux:» lowest 2 bits of address must be 00 2» i.e., treated the same as a 4-byte primitive data type 3 CISCʼFa08

4 Satisfying Alignment with Structures Offsets Within Structure Must satisfy elementʼs alignment requirement Overall Structure Placement Each structure has alignment requirement K Largest alignment of any element Initial address & structure length must be multiples of K struct S1 { char c; int i[2]; double v; } *p; Example (under Windows): K = 8, due to double element c i[0] i[1] v p+0 p+4 p+8 p+16 p+24 Multiple of 4 Multiple of 8 Multiple of 8 Multiple of 8 4 CISCʼFa08

5 Linux vs. Windows Windows (including Cygwin): K = 8, due to double element struct S1 { char c; int i[2]; double v; } *p; Linux: c i[0] i[1] v p+0 p+4 p+8 p+16 p+24 Multiple of 4 Multiple of 8 Multiple of 8 Multiple of 8 K = 4; double treated like a 4-byte data type c i[0] i[1] p+0 p+4 p+8 Multiple of 4 Multiple of 4 Multiple of 4 5 CISCʼFa08 v p+12 p+20 Multiple of 4

6 Overall Alignment Requirement struct S2 { double x; int i[2]; char c; } *p; p must be multiple of: 8 for Windows 4 for Linux x i[0] i[1] c p+0 p+8 p+12 p+16 Windows: p+24 Linux: p+20 struct S3 { float x[2]; int i[2]; char c; p must be multiple of 4 (in either OS) } *p; x[0] x[1] i[0] i[1] p+0 p+4 p+8 p+12 p+16 p+20 c 6 CISCʼFa08

7 Ordering Elements Within Structure struct S4 { char c1; double v; char c2; int i; } *p; 10 bytes wasted space in Windows c1 v p+0 p+8 p+16 p+20 p+24 c2 i struct S5 { double v; char c1; char c2; int i; } *p; 2 bytes wasted space v c1 c2 p+0 p+8 p+12 p+16 i 7 CISCʼFa08

8 Arrays of Structures Principle Allocated by repeating allocation for array type In general, may nest arrays & structures to arbitrary depth struct S6 { short i; float v; short j; } a[10]; a[1].i a[1].v a[1].j a+12 a+16 a+20 a+24 a[0] a[1] a[2] a+0 a+12 a+24 a+36 8 CISCʼFa08

9 Union Allocation Principles Overlay union elements Allocate according to largest element Can only use one field at a time struct S1 { char c; int i[2]; double v; } *sp; union U1 { char c; int i[2]; double v; } *up; (Windows alignment) c i[0] i[1] v up+0 up+4 up+8 c i[0] i[1] v sp+0 sp+4 sp+8 sp+16 sp+24 9 CISCʼFa08

10 CISC 360 Computer Architecture Logic Design Michela Taufer October 14, 2008 Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective, R. Bryant and D. O'Hallaron, Prentice Hall, CS:APP 2003

11 Overview of Logic Design Fundamental Hardware Requirements Communication How to get values from one place to another Computation Storage Bits are Our Friends Everything expressed in terms of values 0 and 1 Communication Low or high voltage on wire Computation Compute Boolean functions Storage Store bits of information 11 CISCʼFa08

12 Digital Signals Voltage Time Use voltage thresholds to extract discrete values from continuous signal Simplest version: 1-bit signal Either high range (1) or low range (0) With guard range between them Not strongly affected by noise or low quality circuit elements Can make circuits simple, small, and fast 12 CISCʼFa08

13 Computing with Logic Gates a b And Or Not out a b out a out out = a && b out = a b out =!a Outputs are Boolean functions of inputs Respond continuously to changes in inputs With some, small delay Rising Delay Falling Delay a && b b Voltage a Time 13 CISCʼFa08

14 Combinational Circuits Acyclic Network Primary Inputs Primary Outputs Acyclic Network of Logic Gates Continously responds to changes on primary inputs Primary outputs become (after some delay) Boolean functions of primary inputs 14 CISCʼFa08

15 Bit Equality a Bit equal HCL Expression eq bool eq = (a&&b) (!a&&!b) b Generate 1 if a and b are equal Hardware Control Language (HCL) Very simple hardware description language Boolean operations have syntax similar to C logical operations Weʼll use it to describe control logic for processors 15 CISCʼFa08

16 Word Equality Word-Level Representation b 31 a 31 b 30 a 30 Bit equal Bit equal eq 31 eq 30 B A = Eq HCL Representation Eq bool Eq = (A == B) b 1 a 1 b 0 a 0 Bit equal Bit equal eq 1 eq 0 32-bit word size HCL representation Equality operation Generates Boolean value 16 CISCʼFa08

17 Bit-Level Multiplexor s Bit MUX HCL Expression b a out bool out = (s&&a) (!s&&b) Control signal s Data signals a and b Output a when s=1, b when s=0 17 CISCʼFa08

18 Word Multiplexor s Word-Level Representation s b 31 out 31 B A MUX Out a 31 b 30 a 30 out 30 HCL Representation int Out = [ s : A; 1 : B; ]; b 0 a 0 out 0 Select input word A or B depending on control signal s HCL representation Case expression Series of test : value pairs Output value for first successful test 18 CISCʼFa08

19 HCL Word-Level Examples Minimum of 3 Words C B A MIN3 Min3 int Min3 = [ A < B && A < C : A; B < A && B < C : B; 1 : C; ]; Find minimum of three input words HCL case expression Final case guarantees match 4-Way Multiplexor s1 s0 D0 D1 D2 D3 MUX4 Out4 int Out4 = [!s1&&!s0: D0;!s1 : D1;!s0 : D2; 1 : D3; ]; Select one of 4 inputs based on two control bits HCL case expression Simplify tests by assuming sequential matching 19 CISCʼFa08

20 Arithmetic Logic Unit Y X A B A L U OF ZF CF X + Y Y X A B A L U OF ZF CF X - Y Y X A B A L U OF ZF CF X & Y Y X A B A L U OF ZF CF X ^ Y Combinational logic Continuously responding to inputs Control signal selects function computed Corresponding to 4 arithmetic/logical operations in Y86 Also computes values for condition codes 20 CISCʼFa08

21 Registers Structure i 7 D C Q+ o 7 i 6 D C Q+ o 6 i 5 D C Q+ o 5 i 4 i 3 D C D C Q+ Q+ o 4 o 3 I O i 2 i 1 D C D C Q+ Q+ o 2 o 1 Clock i 0 D C Q+ o 0 Clock Stores word of data Different from program registers seen in assembly code Collection of edge-triggered latches Loads input on rising edge of clock 21 CISCʼFa08

22 Register Operation State = x State = y Input = y x Output = x Rising clock y Output = y Stores data bits For most of time acts as barrier between input and output As clock rises, loads input 22 CISCʼFa08

23 State Machine Example In Comb. Logic 0 A L U 0 1 MUX Out Accumulator circuit Load or accumulate on each cycle Load Clock Clock Load In Out x 0 x 1 x 2 x 3 x 4 x 5 x 0 x 0 +x 1 x 0 +x 1 +x 2 x 3 x 3 +x 4 x 3 +x 4 +x 5 23 CISCʼFa08

24 Random-Access Memory vala Read ports srca valb A Register file W valw dstw Write port srcb B Stores multiple words of memory Address input specifies which word to read or write Register file Holds values of program registers %eax, %esp, etc. Register identifier serves as address» ID 8 implies no read or write performed Multiple Ports Clock Can read and/or write multiple words in one cycle» Each has separate address and data input/output 24 CISCʼFa08

25 Register File Timing x vala srca valb srcb A B 2 x Register file Reading Like combinational logic Output data generated based on input address After some delay 2 Writing Like register Update only as clock rises 2 x Register file W valw dstw y 2 Rising clock 2 y Register file W valw dstw Clock Clock 25 CISCʼFa08

26 Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool: Boolean a, b, c, int: words A, B, C, Statements Does not specify word size---bytes, 32-bit words, bool a = bool-expr ; int A = int-expr ; 26 CISCʼFa08

27 HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a && b, a b,!a Word Comparisons A == B, A!= B, A < B, A <= B, A >= B, A > B Set Membership A in { B, C, D } Word Expressions» Same as A == B A == C A == D Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, in sequence Return word expression A, B, C, for first successful test 27 CISCʼFa08

28 Summary Computation Performed by combinational logic Computes Boolean functions Continuously reacts to input changes Storage Registers Hold single words Loaded as clock rises Random-access memories Hold multiple words Possible multiple read or write ports Read word when address input changes Write word as clock rises 28 CISCʼFa08

29 Deadlines 7 Oct 14 Lec11 Logic Design Lab 2 7 Oct 16 Lec12 Sequential Implementation 8 Oct 21 Lec13 Pipelined Implementation I 8 Oct 23 Lec14 Pipelined Implementation II 8 (*) Oct 24 Exercises in class in preparation to exam 9 Oct 28 Lec15 Computer Architecture Wrapup 9 Oct 30 Exam II 10 Nov 4 No class 10 Nov 6 Lec16 Program Optimization I 5 4 Lab 3 29 CISCʼFa08