Where Have We Been? Logic Design in HCL. Assembly Language Instruction Set Architecture (Y86) Finite State Machines

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1 Where Have We Been? Assembly Language Instruction Set Architecture (Y86) Finite State Machines States and Transitions Events Where Are We Going? Tracing Instructions at the Register Level Build a CPU! Pipelining 1 Logic Design in HCL Modern Logic Design from hand-designs to synthesized circuits HCL boolean expressions Word-level HCL expressions Sequential Y86 Implementation processing stages hardware structure stage implementation Modern Logic Design Shift from hand-designs to automatic logic synthesis Technology portability Design Documentation Constraint Driven Synthesis Faster design time, easier to maintain HDL (Hardware Description Language) Verilog VHDL Others

2 Modern Logic Design HDL To describe hardware structure Silicon compilers (developed in mid-80s) can compile HDL programs into efficient circuit designs Can describe truth tables, state diagrams, and boolean equations Verilog HDL Language is similar to C, was owned by Cadence, became open in 1990 Most widely used HDL VHDL (Very High Speed HDL) Language is similar to Ada, IEEE standard Complex Example of HDL module my_circuit; title Half-Adder' " input pins A, B pin 3, 5; " output pins SUM, Carry_out pin 15, 18 istype 'com'; equations SUM = (A &!B) (!A & B) ; Carry_out = A & B; end my_circuit; HCL Hardware Control Language Boolean equations Example: 1) boolean function for Figure 4.9 in the text (bit level) bool eq = (a && b) (!a &&!b) 2) multiplexor bool out = (s && a) (!s && b); 3) word level expressions bool Eq = ( A == B) ; A and B are int 4) word level mux int Out = [ s: A; 1: B; ];

3 s A). Bit-level implementation B). Word-level abstraction b 31 out 31 a 31 b 30 out 30 s a 30 B A MUX Out b 0 out 0 int Out = [ s : A; 1 : B; ]; a 0 7 HCL (cont.) Multiplexing functions are described using case expressions Example: Int out = [!s1 &&!s0 : A;!s1 : B; s1 &&!s0 : C; 1 : D; ] HCL does not require the different select expressions to be mutually exclusive. Logically, the selection expressions are evaluated in sequence, and the case for the first one yielding 1 is selected. HCL (cont.) Selecting the maximum of A, B and C Example: Int maximum = [ A<=B && C <= B : B; B<=A && C <= A : A; 1 : C; ] Set membership to compare one signal against a number of possible matching signals bool s1 = code in {2,3} s1 is 1 when code is in the set {2,3} bool s0 = code in {1,3}

4 Set membership example: bool s0 = op_code in {3,4,5} s1 = op_code in {7,8} op_code control s1 s0 Next_ = + 5 or +6 These are Our Y86 Instructions Byte nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V rmmovl ra, D(rB) 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D OPl ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl ra A 0 ra 8 popl ra B 0 ra 8 12 Sequential Y86 Implementation Organizing Processing into stages make all instructions follow a uniform sequence make best use of the hardware Six stages Write back update

5 stage Read the bytes of an instruction from the memory (cache) pointed by. Extracts two 4-bit portions: icode (the instruction code, or OP code) and ifun (the function code). the register specification byte. register operand ra and rb. es the 4-byte constant (immediate value) Calculate the next next = + length_of_the_current_instruction stage / stage Read two operands from register file. stage ALU operation performed (based on ifun) Computes the effective address of a memory operand Increment/decrement stack pointer CC (Condition Code) set Decide whether to branch or not / Write-back/ Update stage stage Read or write data to memory stage Write results back to register file Update stage Set to next

6 Computations in SEQ (Opl) OPl ra, rb ra:rb M1[+1] next = + 2 vala R[rA] valb R[rB] vale valb op vala setcc Not applicable R[rB] vale Tracing the execution of (addl) 0x000: 6023 addl %edx, %ebx icode:ifun M1[]; ra:rb M1[+1]; next = + 2; vala R[rA]; valb R[rB]; vale valb op vala setcc Not applicable R[rB] vale Assume %eip: 0x000 %eax: 0 %ecx: 1 %edx: 100 %ebx: 200 Computations in SEQ (rrmovl) rrmovl ra, rb ra:rb M1[+1] next = + 2 vala R[rA] vale 0 + vala Not applicable R[rB] vale

7 Computations in SEQ (irmovl) irmovl V, rb ra:rb M1[+1] valc M4[+2] next = + 6 vale 0 + valc Not applicable R[rB] vale Tracing the execution of (irmovl) 0x00e: irmovl V, rb ra:rb M1[+1] valc M4[+2] next = + 6 Assume %eip: 0x00e vale 0 + valc Not applicable R[rB] vale Tracing the execution of (irmovl) 0x00e: irmovl V, rb ra:rb M1[+1] valc M4[+2] next = + 6 3:0 8:6 128 (0x80) 0x014 Assume %eip: 0x00e vale 0 + valc Not applicable R[rB] vale 128 %esi 128 0x014

8 Computations in SEQ (rmmovl) rmmovl ra,d(rb) ra:rb M1[+1] valc M4[+2] next = + 6 vala R[rA] valb R[rB] vale valb + valc M4[valE] vala Tracing the execution of (rmmovl) 0x014: rmmovl ra,d(rb) ra:rb M1[+1] valc M4[+2] next = + 6 vala R[rA] valb R[rB] vale valb + valc Assume %eip: 0x014 %eax: 0 %ecx: 1 %edx: 1000 %ebx: 2000 M4[valE] vala Computations in SEQ (mrmovl) mrmovl D(rB), ra ra:rb M1[+1] valc M4[+2] next = + 6 valb R[rB] vale valb + valc valm M4[valE] R[rA] valm

9 Computations in SEQ (pushl) pushl ra ra:rb M1[+1] next = + 2 vala R[rA] valb R[%esp] vale valb + (-4) M4[valE] vala R[%esp] vale Tracing the execution of (pushl) 0x014: a028 pushl ra ra:rb M1[+1] next = + 2 vala R[rA] valb R[%esp] vale valb + (-4) Assume %eip: 0x014 %eax: 0 %ecx: 1 %edx: 1000 %ebx: 2000 %esp: 128 M4[valE] vala R[%esp] vale Computations in SEQ (popl) popl ra ra:rb M1[+1] next = + 2 vala R[%esp] valb R[%esp] vale valb + 4 valm M4[valA] R[%esp] vale R[rA] valm

10 Computations in SEQ (Jxx) Jxx Dest valc M4[+1] next = + 5 Bch Cond(CC, ifun) Bch? valc:next Computations in SEQ (call) Call Dest valc M4[+1] next = + 5 valb R[%esp] vale valb + (-4) M4[valE] next R[%esp] vale valc Computations in SEQ (ret) Ret next = + 1 vala R[%esp] valb R[%esp] vale valb + 4 valm M4[valA] R[%esp] vale valm

11 Tracing the execution of (ret) 0x098: 90 Call Dest next = + 1 vala R[%esp] valb R[%esp] vale valb + 4 9:0 0x Assume %eip: 0x098 %esp: 124 M[128]: 0x28 valm M4[valA] R[%esp] vale valm 0x028 %esp = 128 0x028 Quiz 1) Which instructions have no actions at the Write Back? a) Store (rmmovl) b) Call c) Popl d) Jxx (jmp) 2) Which instructions write two registers at the Write Back a) Pushl b) Popl c) Load (mrmovl) d) Ret 3) What instructions need to use the stage? 41 Build a CPU 43

12 SEQ Hardware Structure WB Instruction memory increment Register file ALU And CC Data 44 SEQ Control Signals WB Icode, ifun, ra, rb, valc Instruction memory increment next srca, srcb Register file Two read ports Two write ports vala, valb ALU And CC Bch Addr, data valm Data next 45 Computation Steps in SEQ Write back Computation Icode, ifun, ra, rb, valc, valp vala, valb, srca, srcb vale, CC Read / write E port/ dste, M port/ dstm 46

13 0x00c Combination Logic CC 100 Addl %edx, %ebx Data Register File write 0x00c 47 Instr valid icode ra, rb, valc ifun Need valc Need regids valp increment Byte 0 Split Align Byte 1-5 Instruction 50 HCL Descriptions for Bool need_regids = [ icode in {RRMOVL, OPL, PUSHL, IRMOVL, RMMOVL, MRMOVL}; Bool need_valc = [ icode in {IRMOVL, RMMOVL, MRMOVL, JMP, CALL} Bool instr_valid =?? icode in 0 to B 51

14 vala valb valm Port A Port B Register File Port M Port E vale dste dstm srca srcb icode 52 ra rb HCL Descriptions for Int srca = [ icode in {RRMOVL, IRMOVL, OPL, PUSHL}: ra; icode in {POPL,RET}: 6 ; /* %esp */ 1 : 8;] Int srcb = [ 53 vale BCond CC ALU ALU func Set CC ALU A ALU B icode ifun valc vala valb 55

15 HCL Descriptions for Int alua = [ icode in {RRMOVL, OPL}: vala; icode in {IRMOVL, RMMOVL, MRMOVL} : valc; icode in {CALL, PUSHL} : -4; icode in {RET, POPL}: 4; Other instructions don t need ALU ] 56 HCL Descriptions for Int alub = [ icode in {RMMOVL, MRMOVL, OPL CALL, PUSHL, RET, POPL}: valb; icode in {RRMOVL, IRMOVL} : 0; other instructions don t need ALU ] Call, ret, push,pop Int alufun = [ icode == OPL : ifun; 1: 0; /* functioning as an adder */ ] Bool setcc = icode in {OPL}; need %esp for valb 57 Update New icode Bch valc valm next 58

16 HCL Descriptions for Update Int new = [ icode in == CALL: valc; Icode == JMP && Bch : valc; icode == RET : valm; 1: next ] 59 General Principles of Pipelining Execution pipeline IF ID EX Mem WB irmovl $2,%3 mrmovl %4, b Je DEST Clock 0 Clock 1 Clock 2 Clock 3 Clock 4 Clock 5 Clock 6 Clock 7 Clock 8 60 Principles of Pipelining Pipelining increases the execution throughput It may also increase latency, due to non-uniform partitioning The effectiveness of pipelining depends on how much data dependency and control dependency. Optimizing compilers schedule code to minimize the impact of data dependency. Some compiler transformations eliminate control dependency. Many Micro-architectural techniques minimize the impact of control dependency 61