Computer Science 104:! Y86 & Single Cycle Processor Design!

Transcription

1 Computer Science 104: Y86 & Single Cycle Processor Design Alvin R. Lebeck Slides based on those from Randy Bryant 1 CS:APP Administrative Homework #4 My office hours today 11:30-12:30 Reading: text CS:APP

2 Bit Equality Bit equal a HCL Expression eq bool eq = (a&&b) (a&&b) b n Generate 1 if a and b are equal Hardware Control Language (HCL) n Very simple hardware description language l Boolean operations have syntax similar to C logical operations n We ll use it to describe control logic for processors 3 CS:APP Word Equality Word-Level Representation b 31 a 31 b 30 Bit equal Bit equal eq 31 eq 30 B A = Eq a 30 HCL Representation Eq bool Eq = (A == B) b 1 a 1 b 0 a 0 Bit equal Bit equal eq 1 eq 0 n 32-bit word size n HCL representation l Equality operation l Generates Boolean value 4 CS:APP

3 Bit-Level Multiplexor s Bit MUX HCL Expression b out bool out = (s&&a) (s&&b) a n Control signal s n Data signals a and b n Output a when s=1, b when s=0 5 CS:APP Word Multiplexor s Word-Level Representation s b 31 out 31 B A MUX Out a 31 b 30 a 30 out 30 HCL Representation int Out = [ s : A; 1 : B; ]; b 0 out 0 n Select input word A or B depending on control signal s n HCL representation l Case expression l Series of test : value pairs l Output value for first a 0 successful test 6 CS:APP

4 HCL Word-Level Examples Minimum of 3 Words C B A MIN3 Min3 int Min3 = [ A < B && A < C : A; B < A && B < C : B; 1 : C; ]; n Find minimum of three input words n HCL case expression n Final case guarantees match 4-Way Multiplexor s1 s0 D0 D1 D2 D3 MUX4 Out4 int Out4 = [ s1&&s0: D0; s1 : D1; s0 : D2; 1 : D3; ]; n Select one of 4 inputs based on two control bits n HCL case expression n Simplify tests by assuming sequential matching 7 CS:APP Random-Access Memory vala Read ports srca valb A Register file valw W dstw Write port srcb B n Stores multiple words of memory l Address input specifies which word to read or write n Register file l Holds values of program registers l %eax, %esp, etc. l Register identifier serves as address» ID 8 implies no read or write performed n Multiple Ports Clock l Can read and/or write multiple words in one cycle» Each has separate address and data input/output 8 CS:APP

5 Register File Timing x 2 vala srca valb srcb A B 2 x Register file Reading n Like combinational logic n Output data generated based on input address l After some delay Writing n Like register n Update only as clock rises 2 x Register file valw W dstw y 2 _ Rising clock _ 2 y Register file valw W dstw Clock Clock 9 CS:APP Instruction Set Architecture Assembly Language View n Processor state l Registers, memory, n Instructions l addl, movl, leal, l How instructions are encoded as bytes Layer of Abstraction n Above: how to program machine l Processor executes instructions in a sequence n Below: what needs to be built l Use variety of tricks to make it run fast l E.g., execute multiple instructions simultaneously Application Program Compiler ISA CPU Design Circuit Design Chip Layout 10 CS:APP OS

6 Y86: A simpler Instruction Set IA32 has too many instructions IA32 has too many quirks Y86 subset of IA32 instructions Y86 simpler enconding than IA32 Y86 easier to reason about -> better for understanding hardware 11 CS:APP Y86 Processor State Program registers %eax %ecx %edx %ebx %esi %edi %esp %ebp Condition codes OF ZF SF PC Memory n Program Registers l Same 8 as with IA32. Each 32 bits n Condition Codes l Single-bit flags set by arithmetic or logical instructions» OF: Overflow ZF: Zero SF:Negative n Program Counter l Indicates address of instruction n Memory l Byte-addressable storage array l Words stored in little-endian byte order 12 CS:APP

7 Y86 Instructions Recall Memory is a Bunch of Bits How do we know if it is an instruction or not? How do we know which instruction, which operands, etc. Format n 1--6 bytes of information read from memory l Can determine instruction length from first byte l Not as many instruction types, and simpler encoding than with IA32 n Each accesses and modifies some part(s) of the program state 13 CS:APP Encoding Registers Each register has 4-bit ID %eax %ecx %edx %ebx n Same encoding as in IA32 %esi %edi %esp %ebp Register ID 8 indicates no register n Will use this in our hardware design in multiple places 14 CS:APP

8 Instruction Example Addition Instruction Generic Form addl ra, rb 6 0 rarb Encoded Representation n Add value in register ra to that in register rb l Store result in register rb l Note that Y86 only allows addition to be applied to register data n Set condition codes based on result n e.g., addl %eax,%esi Encoding: n Two-byte encoding l First byte indicates instruction type l Second byte gives source and destination registers 15 CS:APP Arithmetic and Logical Operations Instruction Code Add addl ra, rb Subtract (ra from rb) And subl ra, rb Function Code 6 0 rarb 6 1 rarb n Refer to generically as OPl n Encodings differ only by function code l Low-order 4 bytes in first instruction word n Set condition codes as side effect andl ra, rb 6 2 rarb Exclusive-Or xorl ra, rb 6 3 rarb 16 CS:APP

9 Move Operations rrmovl ra, rb 2 0 rarb Register --> Register irmovl V, rb rb V Immediate --> Register rmmovl ra, D(rB) 4 0 rarb D Register --> Memory mrmovl D(rB), ra 5 0 rarb D Memory --> Register n Like the IA32 movl instruction n Simpler format for memory addresses n Give different names to keep them distinct 17 CS:APP Move Instruction Examples IA32 Y86 Encoding movl $0xabcd, %edx irmovl $0xabcd, %edx cd ab movl %esp, %ebx rrmovl %esp, %ebx movl -12(%ebp),%ecx movl %esi,0x41c(%esp) mrmovl -12(%ebp),%ecx rmmovl %esi,0x41c(%esp) f4 ff ff ff c movl $0xabcd, (%eax) movl %eax, 12(%eax,%edx) movl (%ebp,%eax,4),%ecx 18 CS:APP

10 Jump Instructions Jump Unconditionally jmp Dest 7 0 Dest Jump When Less or Equal jle Dest 7 1 Dest Jump When Less jl Dest 7 2 Dest Jump When Equal je Dest 7 3 Dest Jump When Not Equal jne Dest 7 4 Dest Jump When Greater or Equal n Refer to generically as jxx n Encodings differ only by function code n Based on values of condition codes n Same as IA32 counterparts n Encode full destination address l Unlike PC-relative addressing seen in IA32 jge Dest 7 5 Dest Jump When Greater jg Dest 7 6 Dest 19 CS:APP Y86 Program Stack Increasing Addresses Stack Bottom Stack Top %esp n Region of memory holding program data n Used in Y86 (and IA32) for supporting procedure calls n Stack top indicated by %esp l Address of top stack element n Stack grows toward lower addresses l Top element is at highest address in the stack l When pushing, must first decrement stack pointer l When popping, increment stack pointer 20 CS:APP

11 Stack Operations pushl ra a 0 ra 8 n Decrement %esp by 4 n Store word from ra to memory at %esp n Like IA32 popl ra b 0 ra 8 n Read word from memory at %esp n Save in ra n Increment %esp by 4 n Like IA32 21 CS:APP Subroutine Call and Return call Dest 8 0 Dest n Push address of next instruction onto stack n Start executing instructions at Dest n Like IA32 ret 9 0 n Pop value from stack n Use as address for next instruction n Like IA32 22 CS:APP

12 Miscellaneous Instructions nop 0 0 n Don t do anything halt 1 0 n Stop executing instructions n IA32 has comparable instruction, but can t execute it in user mode 23 CS:APP Y86 Instruction Set Byte nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V addl 6 0 subl 6 1 andl 6 2 xorl 6 3 rmmovl ra, D(rB) 4 0 ra rb D jmp 7 0 mrmovl D(rB), ra 5 0 ra rb D jle 7 1 OPl ra, rb 6 fn ra rb jl 7 2 jxx Dest 7 fn Dest je 7 3 call Dest 8 0 Dest jne 7 4 ret 9 0 jge 7 5 pushl ra A 0 ra 8 jg 7 6 popl ra B 0 ra 8 24 CS:APP

13 Building Blocks fun Combinational Logic n Compute Boolean functions of inputs n Continuously respond to input changes n Operate on data and implement control A B A L U 0 MUX 1 = Storage Elements n Store bits n Addressable memories n Non-addressable registers n Loaded only as clock rises vala srca valb srcb A B Register file valw W dstw Clock Clock 25 CS:APP SEQ Hardware Structure PC (Abstract) State n Program counter register (PC) n Condition code register (CC) n Register File n Memories l Access same memory space l Data: for reading/writing program data l Instruction: for reading instructions Instruction Flow n Read instruction at address specified by PC n Process through stages n Update program counter Write back Memory Execute Decode Fetch icode, ifun ra,rb valc Instruction memory Data memory PC increment 26 CS:APP PC newpc vale, valm Addr, Data valm Bch CC alua, alub srca, srcb dsta, dstb valp vale ALU vala, valb A B M E Register file

14 SEQ Stages Fetch Decode n Read instruction from instruction memory n If PC points to it, we view it as instruction n Read program registers Execute n Compute value or address Memory n Read or write data Write Back PC n Write program registers n Update program counter Write back Memory Execute Decode Fetch icode, ifun ra,rb valc Instruction memory PC increment 27 CS:APP PC PC newpc vale, valm Addr, Data Bch CC alua, alub srca, srcb dsta, dstb valm Data memory valp vale ALU vala, valb Register A B M file E Instruction Decoding Optional Optional 5 0 ra rb D icode ifun ra rb valc Instruction Format n Instruction byte n Optional register byte icode:ifun ra:rb n Optional constant word valc 28 CS:APP

15 Executing Arith./Logical Operation OPl ra, rb Fetch n Read 2 bytes Decode n Read operand registers Execute n Perform operation n Set condition codes 6 fn rarb Memory n Do nothing Write back n Update register PC Update n Increment PC by 2 29 CS:APP Stage Computation: Arith/Log. Ops Fetch Decode Execute OPl ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC Read instruction byte Read register byte n Formulate instruction execution as sequence of simple steps n Use same general form for all instructions; often called Register Transfer Language (RTL) 30 CS:APP Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Memory Write R[rB] vale Write back result back PC update PC valp Update PC

16 Executing rmmovl rmmovl ra, D(rB) 4 0 rarb D Fetch n Read 6 bytes Decode n Read operand registers Execute n Compute effective address Memory n Write to memory Write back n Do nothing PC Update n Increment PC by 6 31 CS:APP Stage Computation: rmmovl Fetch Decode Execute rmmovl ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 4 [PC+2] valp PC+6 vala R[rA] valb R[rB] vale valb + valc Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address Memory M 4 [vale] vala Write value to memory Write back PC update PC valp Update PC n Use ALU for address computation 32 CS:APP

17 Executing popl popl ra b 0 ra 8 Fetch n Read 2 bytes Decode n Read stack pointer Execute n Increment stack pointer by 4 Memory n Read from old stack pointer Write back n Update stack pointer n Write result to register PC Update n Increment PC by 2 33 CS:APP Stage Computation: popl Fetch Decode Execute popl ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%esp] valb R [%esp] vale valb + 4 Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Memory valm M 4 [vala] Read from stack Write R[%esp] vale Update stack pointer back R[rA] valm PC update PC valp Write back result Update PC n Use ALU to increment stack pointer n Must update two registers l Popped value l New stack pointer 34 CS:APP

18 Executing Jumps jxx Dest 7 fn Dest fall thru: XX XX Not taken target: XX XX Taken Fetch Decode n Read 5 bytes n Increment PC by 5 Memory n Do nothing Write back n Do nothing n Do nothing PC Update Execute n Set PC to Dest if branch n Determine whether to take taken or to incremented PC branch based on jump if not branch condition and condition codes 35 CS:APP Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] Read instruction byte Fetch Decode valc M 4 [PC+1] valp PC+5 Read destination address Fall through address Execute Bch Cond(CC,ifun) Memory Write Take branch? back PC update PC Bch? valc : valp Update PC n Compute both addresses n Choose based on setting of condition codes and branch condition 36 CS:APP

19 Executing call call Dest 8 0 Dest return: XX XX target: XX XX Fetch Decode n Read 5 bytes n Increment PC by 5 n Read stack pointer Execute n Decrement stack pointer by 4 Memory n Write incremented PC to new value of stack pointer Write back n Update stack pointer PC Update n Set PC to Dest 37 CS:APP Stage Computation: call call Dest icode:ifun M 1 [PC] Read instruction byte Fetch Decode Execute valc M 4 [PC+1] valp PC+5 valb R[%esp] vale valb + 4 Read destination address Compute return point Read stack pointer Decrement stack pointer Memory M 4 [vale] valp Write return value on stack Write R[%esp] vale Update stack pointer back PC update PC valc Set PC to destination n Use ALU to decrement stack pointer n Store incremented PC 38 CS:APP

20 Executing ret ret 9 0 return: XX XX Fetch n Read 1 byte Decode n Read stack pointer Execute n Increment stack pointer by 4 Memory n Read return address from old stack pointer Write back n Update stack pointer PC Update n Set PC to return address 39 CS:APP Stage Computation: ret Fetch ret icode:ifun M 1 [PC] Read instruction byte Decode Execute Memory Write back PC update vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale PC valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set PC to return address n Use ALU to increment stack pointer n Read return address from memory 40 CS:APP

21 Computation Steps icode,ifun OPl ra, rb icode:ifun M 1 [PC] Read instruction byte Fetch ra,rb ra:rb M 1 [PC+1] Read register byte valc [Read constant word] valp valp PC+2 Compute next PC Decode vala, srca vala R[rA] Read operand A valb, srcb valb R[rB] Read operand B Execute vale vale valb OP vala Perform ALU operation Cond code Set CC Set condition code register Memory valm [Memory read/write] Write back dste dstm R[rB] vale Write back ALU result [Write back memory result] PC update PC PC valp Update PC n All instructions follow same general pattern n Differ in what gets computed on each step 41 CS:APP Computation Steps Fetch Decode Execute Memory Write back PC update icode,ifun ra,rb valc valp vala, srca valb, srcb vale Cond code valm dste dstm PC call Dest icode:ifun M 1 [PC] valc M 4 [PC+1] valp PC+5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale PC valc Read instruction byte [Read register byte] Read constant word Compute next PC [Read operand A] Read operand B Perform ALU operation [Set condition code reg.] [Memory read/write] [Write back ALU result] Write back memory result Update PC n All instructions follow same general pattern n Differ in what gets computed on each step 42 CS:APP

22 Computed Values Fetch icode ifun Instruction code Instruction function ra Instr. Register A rb Instr. Register B valc valp Instruction constant Incremented PC Execute n vale n Bch Memory ALU result Branch flag n valm Value from memory Decode srca Register ID A srcb Register ID B dste Destination Register E dstm Destination Register M vala Register value A valb Register value B 43 CS:APP Summary Y86: a simpler instruction set than IA32 Data path: the hardware structure (connections) of components and flow of data between and through these components to implement the various instructions. Specifically the fetch/execute cycle. Next Time: Control for the data path 44 CS:APP