Computer Science 104:! Y86 & Single Cycle Processor Design!
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1 Computer Science 104:! Y86 & Single Cycle Processor Design! Alvin R. Lebeck! Slides based on those from Randy Bryant CS:APP! Administrative! 2! CS:APP!
2 Y86 Instruction Set! Byte! nop 0 0 halt 1 0 rrmovl ra, rb! 2 0 ra! rb! irmovl V, rb! rb! V! addl 6 0 subl 6 1 andl 6 2 xorl 6 3 rmmovl ra, D(rB) 4 0 ra! rb! D! jmp 7 0 mrmovl D(rB), ra! 5 0 ra! rb! D! jle fn! ra! rb! jl 7 2 jxx Dest! 7 fn! Dest! je 7 3 call Dest! 8 0 Dest! jne 7 4 ret 9 0 jge 7 5 pushl ra! A 0 ra! 8 jg 7 6 popl ra! B 0 ra! 8 3! CS:APP! Building Blocks! fun! A! B! A! L! U! 0! MUX! =! 1! vala! srca! valb! A! Register! file! valw! W! dstw! srcb! B! Clock! Clock! 4! CS:APP!
3 SEQ Stages! PC! Write back! newpc! vale!,!valm! valm! Memory! Addr!, Data! Data! memory! vale! Bch! CC! alua!,!alub! ALU! vala!,!valb! Decode! Fetch! icode!, ifun! ra!,!!rb! valc! Instruction! memory! srca!,!srcb! dsta!,!dstb! valp! PC! increment! Register! A! B! M! file! E! 5! CS:APP! PC! Executing Arith./Logical Operation! 6 fn! ra!rb! 6! CS:APP!
4 Stage Computation: Arith/Log. Ops! Fetch! icode:ifun M 1 [PC]! ra:rb M 1 [PC+1]! Read instruction byte! Read register byte! Decode! Memory! Write! back! PC update! valp PC+2! vala R[rA]! valb R[rB]! vale valb OP vala! Set CC! R[rB] vale! PC valp! Compute next PC! Read operand A! Read operand B! Perform ALU operation! Set condition code register! Write back result! Update PC! Formulate instruction execution as sequence of simple steps! Use same general form for all instructions! 7! CS:APP! Computation Steps! icode,ifun! icode:ifun M 1 [PC]! Read instruction byte! Fetch! ra,rb! ra:rb M 1 [PC+1]! Read register byte! valc! [Read constant word]! valp! valp PC+2! Compute next PC! Decode! vala, srca! vala R[rA]! Read operand A! valb, srcb! valb R[rB]! Read operand B! vale! vale valb OP vala! Perform ALU operation! Cond code! Set CC! Set condition code register! Memory! valm! [Memory read/write]! Write! back! dste! dstm! R[rB] vale! Write back ALU result! [Write back memory result]! PC update! PC! PC valp! Update PC! All instructions follow same general pattern! Differ in what gets computed on each step! 8! CS:APP!
5 Computation Steps! call Dest! Fetch! Decode! Memory! Write! back! PC update! icode,ifun! ra,rb! valc! valp! vala, srca! valb, srcb! vale! Cond code! valm! dste! dstm! PC! icode:ifun M 1 [PC]! valc M 4 [PC+1]! valp PC+5! valb R[%esp]! vale valb + 4! M 4 [vale] valp! R[%esp] vale! PC valc! Read instruction byte! [Read register byte]! Read constant word! Compute next PC! [Read operand A]! Read operand B! Perform ALU operation! [Set condition code reg.]! [Memory read/write]! [Write back ALU result]! Write back memory result! Update PC! All instructions follow same general pattern! Differ in what gets computed on each step! 9! CS:APP! Computed Values! 10! CS:APP!
6 Hardware Control Language! 11! CS:APP! HCL Operations! 12! CS:APP!
7 SEQ Hardware! 13! CS:APP! Fetch Logic! 14! CS:APP!
8 Fetch Logic! 15! CS:APP! Fetch Control Logic! bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; 16! CS:APP!
9 Decode Logic! 17! CS:APP! A Source! Decode! vala R[rA]! Read operand A! rmmovl ra, D(rB)! Decode! vala R[rA]! Read operand A! Decode! Decode! Decode! popl ra! vala R[%esp]! jxx Dest! call Dest! Read stack pointer! No operand! No operand! Decode! ret vala R[%esp]! Read stack pointer! int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 18! CS:APP!
10 E Destination! Write-back! Write-back! Write-back! Write-back! Write-back! R[rB] vale! rmmovl ra, D(rB)! popl ra! R[%esp] vale! jxx Dest! call Dest! R[%esp] vale! Write back result! None! Update stack pointer! None! Update stack pointer! Write-back! ret R[%esp] vale! Update stack pointer! int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 19! CS:APP! Execute Logic! 20! CS:APP!
11 ALU A Input! vale valb OP vala! Perform ALU operation! rmmovl ra, D(rB)! vale valb + valc! popl ra! vale valb + 4! jxx Dest! call Dest! vale valb + 4! Compute effective address! Increment stack pointer! No operation! Decrement stack pointer! ret vale valb + 4! Increment stack pointer! int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valc; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; 21! # Other instructions don't need ALU CS:APP! ]; ALU Operation! vale valb OP vala! Perform ALU operation! rmmovl ra, D(rB)! vale valb + valc! popl ra! vale valb + 4! jxx Dest! call Dest! vale valb + 4! Compute effective address! Increment stack pointer! No operation! Decrement stack pointer! ret vale valb + 4! Increment stack pointer! int alufun = [ icode == IOPL : ifun; 1 : ALUADD; 22! ]; CS:APP!
12 Memory Logic! 23! CS:APP! Memory Address! Memory! No operation! rmmovl ra, D(rB)! Memory! M 4 [vale] vala! Write value to memory! popl ra! Memory! valm M 4 [vala]! Read from stack! jxx Dest! Memory! No operation! call Dest! Memory! M 4 [vale] valp! Write return value on stack! Memory! ret valm M 4 [vala]! Read return address! int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : vale; icode in { IPOPL, IRET } : vala; # Other instructions don't need address 24! CS:APP! ];
13 Memory Read! Memory! No operation! rmmovl ra, D(rB)! Memory! M 4 [vale] vala! Write value to memory! popl ra! Memory! valm M 4 [vala]! Read from stack! jxx Dest! Memory! No operation! call Dest! Memory! M 4 [vale] valp! Write return value on stack! Memory! ret valm M 4 [vala]! Read return address! bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 25! CS:APP! PC Update Logic! 26! CS:APP!
14 PC Update! PC update! PC update! PC update! PC update! PC update! PC update! PC valp! rmmovl ra, D(rB)! PC valp! popl ra! PC valp! jxx Dest! PC Bch? valc : valp! call Dest! PC valc! ret PC valm! Update PC! Update PC! Update PC! Update PC! Set PC to destination! Set PC to return address! int new_pc = [ icode == ICALL : valc; icode == IJXX && Bch : valc; icode == IRET : valm; 1 : valp; ]; 27! CS:APP! SEQ Operation! 28! CS:APP!
15 SEQ Operation #2! state set according to second irmovl instruction! combinational logic starting to react to state changes! 29! CS:APP! SEQ Operation #3! state set according to second irmovl instruction! combinational logic generates results for addl instruction! 30! CS:APP!
16 SEQ Operation #4! state set according to addl instruction! combinational logic starting to react to state changes! 31! CS:APP! SEQ Operation #5! state set according to addl instruction! combinational logic generates results for je instruction! 32! CS:APP!
17 SEQ Summary! 33! CS:APP!
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