EE 4755 Digital Design Using Hardware Description Languages
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1 EE 4755 Digital Design Using Hardware Description Languages Midterm Exam Review When / Where Monday, 16 October 2017, 9:30-10:20 CDT 225 Tureaud Hall (Here) Conditions Closed Book, Closed Notes Bring one sheet of notes (both sides), 216mm 280mm. No use of communication devices. Format Several problems, short-answer questions. mr 1 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 1
2 Resources Lecture slides and examples used in class: Study Guides Synthesis: Solved tests and homework:. mr 2 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 2
3 Topics for Exam Everything up to but not including sequential logic. Material in lecture slides and homework. mr 3 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 3
4 Study Recommendations Study this semester s homework assignments. Similar problems may appear on the exam. Study previous semesters homework. Solve Old Problems memorizing solutions is not the same as solving. Following and understanding solutions is not the same as solving. Use the solutions for brief hints and to check your own solutions. mr 4 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 4
5 Course Material Areas Verilog The System Verilog language, including structural and behavioral code. Synthesis How hardware is inferred, mapped, and optimized from Verilog. Digital Design The functioning of the circuits covered in class. How to design digital circuits. Tools Understand what simulation and synthesis tools do. mr 5 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 5
6 Verilog Topics Objects See Object Types: variable v net objects. Key difference: variables are assigned, nets are driven (connected to something). Data Types Four-State Integer Types Two-State Integer Types Floating-Point Types String Type mr 6 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 6
7 Integer Data Types Four-State Integer Types: logic, integer, time. Two-State Integer Types: int, bit, byte, shortint, longint. Integer qualifiers: signed, unsigned. mr 7 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 7
8 Real Data Types Real Types: real, shortreal. Type punning: $realtobits, $bitstoreal, etc.. mr 8 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 8
9 Arrays Packed v. Unpacked Arrays wire [7:0] e pluribus unum; wire plain array [7:0]; Element and bit numbering: wire [7:0] color; wire [0:7] colour; Static, Dynamic, and Associative arrays. mr 9 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 9
10 Modules Port and parameter declaration. Module and primitive instantiation. Object declarations. Continuous assign. Procedural code. Generate statements. mr 10 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 10
11 Procedural Code Execution of initial, always, and always comb. Delays (e.g., #5). Event controls posedge clk)). Blocking v. non-blocking assignment. mr 11 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 11
12 Elaboration and Generate Statements Elaboration-time constants. Difference between a module parameter and a port. Generate Statements Difference between generate if and procedural if. Difference between generate for and procedural for. mr 12 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 12
13 Emphases, Key Skills Verilog Key Skills Given a design in one form, write design in another: Explicit Structural Implicit Structural Synthesizable Behavioral Logic Diagram Use generate statements to interconnect modules. Use generate statements in recursive construction of trees. mr 13 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 13
14 Synthesis Key Skills Given Verilog code: Show inferred hardware (before optimization). Show expected optimizations. mr 14 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 14
15 Logic Design Skills Given a design, be able to: Compute Cost Compute Delay mr 15 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 15
16 Synthesis Topics Synthesis Topics Understand what is done during inference, optimization, technology mapping. Inference of combinational logic. Optimization of combinational logic. mr 16 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 16
17 Digital Design Topics Digital Design Topics Common Components Multiplexor Binary Full Adder, Ripple Adder Integer Equality and Magnitude Comparison Common Component Skills Show how to implement using basic gates. Know how to optimize for special cases (a constant input, etc.). mr 17 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 17
18 Cost and Delay Estimation Simple Cost Model Cost of n-input AND and OR gates are n 1 units. Inverters (NOT gates) are free. Delay of n-input gate is lgn units. mr 18 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 18
19 Tools Synthesis (RTL Encounter). read hdl, elaborate define clock synthesize -to generic synthesize -to mapped report area, timing mr 19 LSU EE 4755 Lecture Transparency. Formatted 9:23, 13 October 2017 from lslimr. mr 19
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