Computer Science 104:! Y86 & Single Cycle Processor Design!
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1 Computer Science 104:! Y86 & Single Cycle Processor Design! Alvin R. Lebeck! Slides based on those from Randy Bryant 1! CS:APP! CS:APP! Administrative! 2! CS:APP!
2 Instruction Set Architecture! Application! Program! Compiler! OS! ISA! CPU! Design! Circuit! Design! Chip! Layout! 3! CS:APP! Y86: A simpler Instruction Set! 4! CS:APP!
3 Y86 Processor State! Program registers! %eax %ecx %edx %ebx %esi %edi %esp %ebp Condition codes! OF ZF SF PC! Memory! Program Registers! Same 8 as with IA32. Each 32 bits! Condition Codes! Single-bit flags set by arithmetic or logical instructions!» OF: Overflow!ZF: Zero!SF:Negative! Program Counter! Indicates address of instruction! Memory! Byte-addressable storage array! Words stored in little-endian byte order! 5! CS:APP! Y86 Instructions! 6! CS:APP!
4 Encoding Registers! %eax %ecx %edx %ebx %esi %edi %esp %ebp ! CS:APP! Instruction Example! Generic Form! Encoded Representation! addl ra, rb! 6 0 ra!rb! 8! CS:APP!
5 Arithmetic and Logical Operations! Instruction Code! Add! addl ra, rb! Subtract (ra from rb)! And! subl ra, rb! Function Code! 6 0 ra!rb! 6 1 ra!rb! Refer to generically as OPl! Encodings differ only by function code! Low-order 4 bytes in first instruction word! Set condition codes as side effect! andl ra, rb! 6 2 ra!rb! Exclusive-Or! xorl ra, rb! 6 3 ra!rb! 9! CS:APP! Move Operations! rrmovl ra, rb! 2 0 ra!rb! Register --> Register! irmovl V, rb! rb! V! Immediate --> Register! rmmovl ra, D(rB)! 4 0 ra!rb! D! Register --> Memory! mrmovl D(rB), ra 5 0 ra!rb! D! Memory --> Register! Like the IA32 movl instruction! Simpler format for memory addresses! Give different names to keep them distinct! 10! CS:APP!
6 Move Instruction Examples! IA32! Y86! Encoding! movl $0xabcd, %edx! irmovl $0xabcd, %edx! cd ab 00 00! movl %esp, %ebx! rrmovl %esp, %ebx! 20 43! movl -12(%ebp),%ecx! movl %esi,0x41c(%esp)! mrmovl -12(%ebp),%ecx rmmovl %esi,0x41c(%esp) f4 ff ff ff! c ! movl $0xabcd, (%eax)! movl %eax, 12(%eax,%edx)! movl (%ebp,%eax,4),%ecx!!!!!!! 11! CS:APP! Jump Instructions! Jump Unconditionally! jmp Dest! 7 0 Dest! Jump When Less or Equal! jle Dest! 7 1 Dest! Jump When Less! jl Dest! 7 2 Dest! Jump When Equal! je Dest! 7 3 Dest! Jump When Not Equal! jne Dest! 7 4 Dest! Jump When Greater or Equal! Refer to generically as jxx! Encodings differ only by function code! Based on values of condition codes! Same as IA32 counterparts! Encode full destination address! Unlike PC-relative addressing seen in IA32! jge Dest! 7 5 Dest! Jump When Greater! jg Dest! 7 6 Dest! 12! CS:APP!
7 Y86 Program Stack! Stack Bottom! Region of memory holding program data! Used in Y86 (and IA32) for supporting procedure calls! Increasing! Addresses! Stack Top! %esp Stack top indicated by %esp Address of top stack element! Stack grows toward lower addresses! Top element is at highest address in the stack! When pushing, must first decrement stack pointer! When popping, increment stack pointer! 13! CS:APP! Stack Operations! pushl ra! a 0 ra! 8 Decrement %esp by 4! Store word from ra to memory at %esp Like IA32! popl ra! b 0 ra! 8 Read word from memory at %esp Save in ra! Increment %esp by 4! Like IA32! 14! CS:APP!
8 Subroutine Call and Return! call Dest! 8 0 Dest! Push address of next instruction onto stack! Start executing instructions at Dest! Like IA32! ret! 9 0 Pop value from stack! Use as address for next instruction! Like IA32! 15! CS:APP! Miscellaneous Instructions! nop! 0 0 Donʼt do anything! halt! 1 0 Stop executing instructions! IA32 has comparable instruction, but canʼt execute it in user mode! 16! CS:APP!
9 Y86 Instruction Set! Byte! nop 0 0 halt 1 0 rrmovl ra, rb! 2 0 ra! rb! irmovl V, rb! rb! V! addl 6 0 subl 6 1 andl 6 2 xorl 6 3 rmmovl ra, D(rB) 4 0 ra! rb! D! jmp 7 0 mrmovl D(rB), ra! 5 0 ra! rb! D! jle 7 1 OPl ra, rb! 6 fn! ra! rb! jl 7 2 jxx Dest! 7 fn! Dest! je 7 3 call Dest! 8 0 Dest! jne 7 4 ret 9 0 jge 7 5 pushl ra! A 0 ra! 8 jg 7 6 popl ra! B 0 ra! 8 17! CS:APP! Building Blocks! fun! A! B! A! L! U! 0! MUX! =! 1! vala! srca! valb! A! Register! file! valw! W! dstw! srcb! B! Clock! Clock! 18! CS:APP!
10 SEQ Hardware Structure PC! (Abstract)! Write back! Memory! newpc! vale!,!valm! Addr!, Data! valm! Data! memory! vale! Bch! CC! alua!,!alub! ALU! vala!,!valb! icode!, ifun! ra!,!!rb! valc! Instruction! memory! srca!,!srcb! dsta!,!dstb! valp! PC! increment! Register! A! B! M! file! E! 19! CS:APP! PC! SEQ Stages! PC! Write back! newpc! vale!,!valm! valm! Memory! Addr!, Data! Data! memory! vale! Bch! CC! alua!,!alub! ALU! icode!, ifun! ra!,!!rb! valc! Instruction! memory! srca!,!srcb! dsta!,!dstb! vala!,!valb! valp! PC! increment! A! B! M! E! Register! file! 20! CS:APP! PC!
11 Instruction Decoding! Optional! Optional! 5 0 ra! rb! D! icode! ifun! ra! rb! valc! 21! CS:APP! Executing Arith./Logical Operation! OPl ra, rb! 6 fn! ra!rb! 22! CS:APP!
12 Stage Computation: Arith/Log. Ops! OPl ra, rb! icode:ifun M 1 [PC]! ra:rb M 1 [PC+1]! Read instruction byte! Read register byte! Memory! Write! back! PC update! valp PC+2! vala R[rA]! valb R[rB]! vale valb OP vala! Set CC! R[rB] vale! PC valp! Compute next PC! Read operand A! Read operand B! Perform ALU operation! Set condition code register! Write back result! Update PC! Formulate instruction execution as sequence of simple steps! Use same general form for all instructions; often called Register Transfer Language (RTL)! 23! CS:APP! Executing rmmovl rmmovl ra, D(rB)! 4 0 ra!rb! D! 24! CS:APP!
13 Stage Computation: rmmovl rmmovl ra, D(rB)! icode:ifun M 1 [PC]! ra:rb M 1 [PC+1]! valc M 4 [PC+2]! valp PC+6! vala R[rA]! valb R[rB]! vale valb + valc! Read instruction byte! Read register byte! Read displacement D! Compute next PC! Read operand A! Read operand B! Compute effective address! Memory! M 4 [vale] vala! Write value to memory! Write! back! PC update! PC valp! Update PC! Use ALU for address computation! 25! CS:APP! Executing popl popl ra! b 0 ra! 8 26! CS:APP!
14 Stage Computation: popl popl ra! icode:ifun M 1 [PC]! ra:rb M 1 [PC+1]! Read instruction byte! Read register byte! valp PC+2! vala R[%esp]! valb R [%esp]! vale valb + 4! Compute next PC! Read stack pointer! Read stack pointer! Increment stack pointer! Memory! valm M 4 [vala]! Read from stack! Write! R[%esp] vale! Update stack pointer! back! R[rA] valm! PC update! PC valp! Write back result! Update PC! Use ALU to increment stack pointer! Must update two registers! Popped value! 27! New stack pointer! CS:APP! Executing Jumps! jxx Dest! 7 fn! Dest! fall thru:! XX XX Not taken! target:! XX XX Taken! 28! CS:APP!
15 Stage Computation: Jumps! jxx Dest! icode:ifun M 1 [PC]! valc M 4 [PC+1]! valp PC+5! Read instruction byte! Read destination address! Fall through address! Memory! Write! back! PC update! Bch Cond(CC,ifun)! PC Bch? valc : valp! Take branch?! Update PC! Compute both addresses! Choose based on setting of condition codes and branch condition! 29! CS:APP! Executing call call Dest! 8 0 Dest! return:! XX XX target:! XX XX 30! CS:APP!
![Stage Computation: call call Dest! icode:ifun M 1 [PC]! Read instruction byte! valc M 4 [PC+1]! valp PC+5! valb R[%esp]! vale valb + 4! Read destination address! Compute return point!](/docs-images/75/72669841/images/16-0.jpg "Read stack pointer! Decrement stack pointer! Memory! M 4 [vale] valp! Write return value on stack! Write! R[%esp] vale! Update stack pointer! back! PC update! PC valc! Set PC to destination!")
16 Stage Computation: call call Dest! icode:ifun M 1 [PC]! Read instruction byte! valc M 4 [PC+1]! valp PC+5! valb R[%esp]! vale valb + 4! Read destination address! Compute return point! Read stack pointer! Decrement stack pointer! Memory! M 4 [vale] valp! Write return value on stack! Write! R[%esp] vale! Update stack pointer! back! PC update! PC valc! Set PC to destination! Use ALU to decrement stack pointer! Store incremented PC! 31! CS:APP! Executing ret ret! 9 0 return:! XX XX 32! CS:APP!
17 Stage Computation: ret ret icode:ifun M 1 [PC]! Read instruction byte! Memory! Write! back! PC update! vala R[%esp]! valb R[%esp]! vale valb + 4! valm M 4 [vala]! R[%esp] vale! PC valm! Read operand stack pointer! Read operand stack pointer! Increment stack pointer! Read return address! Update stack pointer! Set PC to return address! Use ALU to increment stack pointer! Read return address from memory! 33! CS:APP! Computation Steps! icode,ifun! OPl ra, rb! icode:ifun M 1 [PC]! Read instruction byte! ra,rb! ra:rb M 1 [PC+1]! Read register byte! valc! [Read constant word]! valp! valp PC+2! Compute next PC! vala, srca! vala R[rA]! Read operand A! valb, srcb! valb R[rB]! Read operand B! vale! vale valb OP vala! Perform ALU operation! Cond code! Set CC! Set condition code register! Memory! valm! [Memory read/write]! Write! back! dste! dstm! R[rB] vale! Write back ALU result! [Write back memory result]! PC update! PC! PC valp! Update PC! All instructions follow same general pattern! Differ in what gets computed on each step! 34! CS:APP!
18 Computation Steps! call Dest! Memory! Write! back! PC update! icode,ifun! ra,rb! valc! valp! vala, srca! valb, srcb! vale! Cond code! valm! dste! dstm! PC! icode:ifun M 1 [PC]! valc M 4 [PC+1]! valp PC+5! valb R[%esp]! vale valb + 4! M 4 [vale] valp! R[%esp] vale! PC valc! Read instruction byte! [Read register byte]! Read constant word! Compute next PC! [Read operand A]! Read operand B! Perform ALU operation! [Set condition code reg.]! [Memory read/write]! [Write back ALU result]! Write back memory result! Update PC! All instructions follow same general pattern! Differ in what gets computed on each step! 35! CS:APP! Computed Values! 36! CS:APP!
19 Summary! 37! CS:APP!
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