CSC 252: Computer Organization Spring 2018: Lecture 11
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- Angelina Griffith
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1 CSC 252: Computer Organization Spring 2018: Lecture 11 Instructor: Yuhao Zhu Department of Computer Science University of Rochester Action Items: Assignment 3 is due March 2, midnight
2 Announcement Programming Assignment 3 is out Due on March 2, midnight due 2
3 Announcement There is another faculty candidate talk Monday, noon, this room, with food 3
4 So far in 252 C Program Assembly Program Instruction Set Architecture Processor Microarchitecture Circuits ISA is the interface between assembly programs and microarchitecture Assembly view: How to program the machine, based on instructions and processor states (registers, memory, condition codes, etc.)? Instructions are executed sequentially Microarchitecture view: What hardware needs to be built to run assembly programs? How to run programs as fast (energy-efficient) as possible? 4
5 Today: Processor Microarchitecture The Y86-64 ISA: Simplified version of x86-64 How an assembler works Sequential, single-cycle microarchitecture implementation Basic idea Hardware implementation 5
6 6 How are Instructions Encoded in Binary? Remember that in a stored program computer, instructions are stored in memory as bits (just like data) Each instruction is fetched (according to the address specified in the PC), decoded, and executed by the CPU The ISA defines the format of an instruction (syntax) and its meaning (semantics) Each instruction has two major fields: opcode and operand The OPCODE field says what the instruction does (e.g. ADD) The OPERAND field(s) say where to find inputs and outputs
7 Y86-64 Instruction Set Byte halt 0 0 nop 1 0 cmovxx ra, rb 2 fn ra rb irmovq V, rb 3 0 F rb V rmmovq ra, D(rB) 4 0 ra rb D mrmovq D(rB), ra 5 0 ra rb D OPq ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushq ra A 0 ra F popq ra B 0 ra F 7
8 Y86-64 Instruction Set Byte halt 0 0 nop 1 0 cmovxx ra, rb 2 fn ra rb irmovq V, rb 3 0 F rb V rmmovq ra, D(rB) 4 0 ra rb D mrmovq D(rB), ra 5 0 ra rb D OPq ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest addq 6 0 subq 6 1 andq 6 2 xorq 6 3 ret 9 0 pushq ra A 0 ra F popq ra B 0 ra F 8
9 Y86-64 Instruction Set Byte jmp 97 0 halt 0 0 nop 1 0 cmovxx ra, rb 2 fn ra rb irmovq V, rb 3 0 F rb V rmmovq ra, D(rB) 4 0 ra rb D mrmovq D(rB), ra 5 0 ra rb D jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 OPq ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushq ra A 0 ra F popq ra B 0 ra F 9
10 10 Encoding Registers Each register has 4-bit ID Same encoding as in x86-64 Register ID 15 (0xF) indicates no register Will use this in our hardware design in multiple places %rax 0 %r8 8 %rcx 1 %r9 9 %rdx 2 %r10 A %rbx 3 %r11 B %rsp 4 %r12 C %rbp 5 %r13 D %rsi 6 %r14 E %rdi 7 No Register F
11 11 Instruction Example Addition Instruction addq ra, rb 6 0 ra rb Add value in register ra to that in register rb Store result in register rb Note that Y86-64 only allows addition to be applied to register data Set condition codes based on result e.g., addq %rax,%rsi Encoding: Two-byte encoding First indicates instruction type Second gives source and destination registers
12 11 Instruction Example Addition Instruction Assembly Form addq ra, rb 6 0 ra rb Add value in register ra to that in register rb Store result in register rb Note that Y86-64 only allows addition to be applied to register data Set condition codes based on result e.g., addq %rax,%rsi Encoding: Two-byte encoding First indicates instruction type Second gives source and destination registers
13 11 Instruction Example Addition Instruction Assembly Form Encoded Representation addq ra, rb 6 0 ra rb Add value in register ra to that in register rb Store result in register rb Note that Y86-64 only allows addition to be applied to register data Set condition codes based on result e.g., addq %rax,%rsi Encoding: Two-byte encoding First indicates instruction type Second gives source and destination registers
14 12 Arithmetic and Logical Operations Add addq ra, rb 6 0 ra rb Subtract (ra from rb) subq ra, rb 6 1 ra rb Refer to generically as OPq Encodings differ only by function code Low-order 4 bytes in first instruction word Set condition codes as side effect And andq ra, rb 6 2 ra rb Exclusive-Or xorq ra, rb 6 3 ra rb
15 12 Arithmetic and Logical Operations Add addq ra, rb 6 0 ra rb Subtract (ra from rb) And Function Code subq ra, rb 6 1 ra rb andq ra, rb 6 2 ra rb Refer to generically as OPq Encodings differ only by function code Low-order 4 bytes in first instruction word Set condition codes as side effect Exclusive-Or xorq ra, rb 6 3 ra rb
16 12 Arithmetic and Logical Operations Instruction Code Add addq ra, rb 6 0 ra rb Subtract (ra from rb) And Function Code subq ra, rb 6 1 ra rb andq ra, rb 6 2 ra rb Refer to generically as OPq Encodings differ only by function code Low-order 4 bytes in first instruction word Set condition codes as side effect Exclusive-Or xorq ra, rb 6 3 ra rb
17 13 Move Operations Register Register rrmovq ra, rb 2 0 ra rb Immediate Register irmovq V, rb 3 0 F rb V Register Memory rmmovq ra, D(rB) 4 0 ra rb D Memory Register mrmovq D(rB), ra 5 0 ra rb D Like the x86-64 movq instruction Simpler format for memory addresses Give different names to keep them distinct
18 14 Jump Instructions Jump Unconditionally jmp Dest 7 0 Jump When Less or Equal jle Dest 7 1 Jump When Less jl Dest 7 2 Jump When Equal je Dest 7 3 Jump When Not Equal jne Dest 7 4 Jump When Greater or Equal jge Dest 7 5 Jump When Greater jg Dest 7 6 Dest Dest Dest Dest Dest Dest Dest
19 15 Stack Operations pushq ra A 0 ra F Decrement %rsp by 8 Store word from ra to memory at %rsp Like x86-64 popq ra B 0 ra F Read word from memory at %rsp Save in ra Increment %rsp by 8 Like x86-64
20 16 Subroutine Call and Return call Dest 8 0 Dest Push address of next instruction onto stack Start executing instructions at Dest Like x86-64 ret 9 0 Pop value from stack Use as address for next instruction Like x86-64
21 17 Miscellaneous Instructions nop 1 0 Don t do anything halt 0 0 Stop executing instructions x86-64 has comparable instruction, but can t execute it in user mode We will use it to stop the simulator Encoding ensures that program hitting memory initialized to zero will halt
22 18 Status Conditions Mnemonic Code AOK 1 Mnemonic Code HLT 2 Mnemonic Code ADR 3 Mnemonic Code INS 4 Normal operation Halt instruction encountered Bad address (either instruction or data) encountered Invalid instruction encountered Desired Behavior If AOK, keep going Otherwise, stop program execution
23 How Does An Assemble Work? Translates assembly code to binary-encode Reads assembly program line by line, and translates according to the instruction format defined by an ISA Add addq ra, rb 6 0 ra rb It sometimes needs to make two passes on the assembly program to resolve forward references E.g., forward branch target address Jump Unconditionally jmp Dest 7 0 Dest 19
24 Today: Processor Microarchitecture The Y86-64 ISA: Simplified version of x86-64 How an assembler works Sequential, single-cycle microarchitecture implementation Basic idea Hardware implementation 20
25 21 Basic Principles for a Sequential Implementation Principles: Execute each instruction one at a time, one after another Express every instruction as series of simple steps Dedicated hardware structure for completing each step Follow same general flow for each instruction type : Read instruction from instruction memory Decode: Read program registers Execute: Compute value or address Memory: Read or write data Write Back: Write program registers PC: Update program counter
26 22 Executing Arith./Logical Operation OPq ra, rb 6 fn ra rb Read 2 bytes Decode Read operand registers Execute Perform operation Memory Do nothing Write back Update register PC Update Increment PC by 2 Set condition codes
27 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb OPq ra, rb
28 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb OPq ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 Read instruction byte Read register byte Compute next PC
29 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb Decode OPq ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] Read instruction byte Read register byte Compute next PC Read operand A Read operand B
30 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb Decode Execute OPq ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC Read instruction byte Read register byte Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register
31 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb Decode Execute Memory OPq ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC Read instruction byte Read register byte Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register
32 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb Decode Execute Memory Write back OPq ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale Read instruction byte Read register byte Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Write back result
33 23 Stage Computation: Arith/Log. Ops OPq ra, rb 6 fn ra rb Decode Execute Memory Write back PC update OPq ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale PC valp Read instruction byte Read register byte Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Write back result Update PC
34 24 Executing rmmovq rmmovq ra, D(rB) 4 0 ra rb D Read 10 bytes Decode Read operand registers Execute Compute effective address: R[rB] + D Memory Write R[rA] to to memory at address R[rB] + D Write back Do nothing PC Update Increment PC by 10
35 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D rmmovq ra, D(rB)
36 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D rmmovq ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 8 [PC+2] valp PC+10 Read instruction byte Read register byte Read displacement D Compute next PC
37 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D Decode rmmovq ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 8 [PC+2] valp PC+10 vala R[rA] valb R[rB] Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B
38 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D Decode Execute rmmovq ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 8 [PC+2] valp PC+10 vala R[rA] valb R[rB] vale valb + valc Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address
39 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D Decode Execute Memory rmmovq ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 8 [PC+2] valp PC+10 vala R[rA] valb R[rB] vale valb + valc M 8 [vale] vala Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address Write value to memory
40 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D Decode Execute Memory Write back rmmovq ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 8 [PC+2] valp PC+10 vala R[rA] valb R[rB] vale valb + valc M 8 [vale] vala Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address Write value to memory
41 25 Stage Computation: rmmovq rmmovq ra, D(rB) 4 0 ra rb D Decode Execute Memory Write back PC update rmmovq ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 8 [PC+2] valp PC+10 vala R[rA] valb R[rB] vale valb + valc M 8 [vale] vala PC valp Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address Write value to memory Update PC
42 26 Executing popq popq ra b 0 ra 8 Read 2 bytes Decode Read stack pointer (%rsp) Execute Increment stack pointer by 8 Memory Read from the top of the stack from memory Write back Update stack pointer Write result to register PC Update Increment PC by 2
43 27 Stage Computation: popq popq ra b 0 ra 8 popq ra
44 27 Stage Computation: popq popq ra b 0 ra 8 popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 Read instruction byte Read register byte Compute next PC
45 27 Stage Computation: popq popq ra b 0 ra 8 Decode popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%rsp] valb R[%rsp] Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer
46 27 Stage Computation: popq popq ra b 0 ra 8 Decode Execute popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%rsp] valb R[%rsp] vale valb + 8 Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer
47 27 Stage Computation: popq popq ra b 0 ra 8 Decode Execute Memory popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%rsp] valb R[%rsp] vale valb + 8 valm M 8 [vala] Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Read from stack
48 27 Stage Computation: popq popq ra b 0 ra 8 Decode Execute Memory Write back popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%rsp] valb R[%rsp] vale valb + 8 valm M 8 [vala] R[%rsp] vale R[rA] valm Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer Write back result
49 27 Stage Computation: popq popq ra b 0 ra 8 Decode Execute Memory Write back PC update popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%rsp] valb R[%rsp] vale valb + 8 valm M 8 [vala] R[%rsp] vale R[rA] valm PC valp Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer Write back result Update PC
50 Stage Computation: popq popq ra b 0 ra 8 Decode Execute popq ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[%rsp] valb R[%rsp] vale valb + 8 Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Memory Write back PC update valm M 8 [vala] R[%rsp] vale R[rA] valm PC valp Read from stack Update stack pointer Write back result Update PC Must update two registers (Register file must have two write ports) Popped value and New stack pointer 27
51 28 Executing Jumps jxx Dest 7 fn Dest fall thru: XX XX Not taken target: XX XX Taken Read 9 bytes Increment PC by 9 Decode Do nothing Execute Determine whether to take branch based on jump condition and condition codes Memory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch
52 29 Stage Computation: Jumps jxx Dest Compute both addresses Choose based on setting of condition codes and branch condition
53 29 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Fall through address Compute both addresses Choose based on setting of condition codes and branch condition
54 29 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Fall through address Decode Compute both addresses Choose based on setting of condition codes and branch condition
55 29 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Fall through address Decode Execute Cnd Cond(CC,ifun) Take branch? Compute both addresses Choose based on setting of condition codes and branch condition
56 29 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Fall through address Decode Execute Memory Cnd Cond(CC,ifun) Take branch? Compute both addresses Choose based on setting of condition codes and branch condition
57 29 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Fall through address Decode Execute Memory Write back Cnd Cond(CC,ifun) Take branch? Compute both addresses Choose based on setting of condition codes and branch condition
58 29 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Fall through address Decode Execute Memory Write back PC update Cnd Cond(CC,ifun) PC Cnd? valc : valp Take branch? Update PC Compute both addresses Choose based on setting of condition codes and branch condition
59 30 Executing call call Dest 8 0 Dest return: XX XX target: XX XX Read 9 bytes Increment PC by 9 (return address) Decode Read stack pointer (%rsp) Execute Decrement stack pointer by 8 Memory Write incremented PC (i.e., return address) to top of the stack in the memory Write back Update stack pointer PC Update Set PC to Dest
60 31 Stage Computation: call call Dest
61 31 Stage Computation: call call Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 Read instruction byte Read destination address Compute return point
62 31 Stage Computation: call Decode call Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 valb R[%rsp] Read instruction byte Read destination address Compute return point Read stack pointer
63 31 Stage Computation: call Decode Execute call Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 valb R[%rsp] vale valb + 8 Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer
64 31 Stage Computation: call Decode Execute Memory call Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 valb R[%rsp] vale valb + 8 M 8 [vale] valp Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer Write return value on stack
65 31 Stage Computation: call Decode Execute Memory Write back call Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 valb R[%rsp] vale valb + 8 M 8 [vale] valp R[%rsp] vale Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer Write return value on stack Update stack pointer
66 31 Stage Computation: call Decode Execute Memory Write back PC update call Dest icode:ifun M 1 [PC] valc M 8 [PC+1] valp PC+9 valb R[%rsp] vale valb + 8 M 8 [vale] valp R[%rsp] vale PC valc Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer Write return value on stack Update stack pointer Set PC to destination
67 Today: Processor Microarchitecture The Y86-64 ISA: Simplified version of x86-64 How an assembler works Sequential, single-cycle microarchitecture implementation Basic idea Hardware implementation 32
68 33 Building Blocks Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control = 0 MUX 1 A B fun A L U Storage Elements vala Store bits Addressable memories Non-addressable registers srca valb srcb A B Register file W valw dstw Clock Loaded only as clock rises Clock
69 34 Microarchitecture Overview Storage (All updated as clock rises) PC register Cond. Code register Combinational logic Read Write Data memory Register file Combinational Logic ALU CC 100 Read ports Data memory Register file %rbx = 0x100 Write ports Control logic Memory reads Instruction memory Register file Data memory PC 0x014
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