Computing to the Energy and Performance Limits with Heterogeneous CPU-FPGA Devices. Dr Jose Luis Nunez-Yanez University of Bristol

Transcription

1 Computing to the Energy and Performance Limits with Heterogeneous CPU-FPGA Devices Dr Jose Luis Nunez-Yanez University of Bristol

2 Power and energy savings at run-time Power = α.c.v 2.f+g1.V 3 Energy = Power * T 1. DVFS (Dynamic Voltage and Frequency Scaling) : open-loop e.g. AMD cool&quiet, Intel SpeedStep 2. AVS (Adaptive Voltage Scaling) closed-loop e.g ARM Razor 3. AVLS (Adaptive Voltage and Logic Scaling) in reconfigurable chips : FPGAs? Power/ Voltage and Frequency relations : Source Intel

3 Adaptive Voltage Scaling tool flow Tool flow and IP blocks control the frequency and voltage of the device and detect optimal operational points at run-time using insitu detectors. The proposed approach works in a variation-aware closed-loop configuration so it is sensitive to temperature and process variations. The flow has been ported to Vivado and it is based on three phases. Phase 3 is done with incremental P&R. SYN.VHD.V source HLS High Level Synthesis OpenCL, C++ source v.vhd netlist Elongate Elongate component library MAP v.vhd netlist User constraints PLACE & ROUTE 1 Timing information 3 Circuit description BITGEN.BIT bitstream 3 3 Elongate implementation flow

4 Timing detectors for logic Soft-macro Detectors guarantee that the path of the slow flip-flop (SFF) slightly longer than main flip-flop (MFF). XOR Detector Output Discrepancies between MFF and SFF are detector in XOR and communicated to DFS (Dynamic Frequency Scaling) unit. 0/1 Generate 0 SFF MFF replicates the functionality of the original flip-flop in the critical path. 0/1 D Input Generate 1 MFF Q Output Logic timing detector

5 EFF control I2C controller System architecture Memory devices ZYNQ boundary UART I/O periph erals Application Processing Unit (Cortex A9 MP) (LPDDR2, DDR3, DDR2) Memory Controller PS voltage domain I2C/PMBUS AXI Interconnect CLK adaptation control MMCM (Mixed Mode Clock Manager) XADC (temperature monitor) DFS Adaptive clk PLL (phase control) Phase clk EFF EFF EFF EFF In-situ detector status User IP block EFF PL voltage domain LEDS (locked, EFF firing) ARM CPU control the Elongate IP

6 Case study: Video Fusion Video fusion of visible and thermal imagery provides a method to combine complementary information for better data analysis. The prototype system uses two cameras interfaced to a Zynqbased board that combines an dual-core ARM processor and a FPGA fabric in the same chip. Fig. 1 Fusion with wavelets Fig. 2 Prototype System

7 percentage Fusion algorithm with DT-CWT DT-CWT algorithm developed in the group as offering good quality of results in presence of noisy input. The forward and reversed DT-CWT represent around 70% of total complexity and are selected as candidates for acceleration. System operates three times faster (amdahl law) but hardware is too fast and needs to wait for data to be prepared by the processor Fig. 3 Fusion with DT-CWT ARM profiling functions Fig. 4 Profiling results

8 Hardware and Linux driver development Hardware accelerator for wavelets developed using high-level synthesis (e.g. Vivado HLS). Processor needs to reserved memory area in kernel space and move pixel data so that it is accessible to the accelerator. Heterogeneous hardware overview User memcpy to buffer 2 App check for accelerator completion and activate User memcpy from buffer 1 User memcpy to buffer 1 App check for accelerator completion and activate User memcpy from buffer 2 Double buffering so that data preparation by processor and data processing by accelerator overlap. Hardware Memcpy from 1 to BRAM Processing Hardware Memcpy from BRAM to 1 Hardware Memcpy from 2 to BRAM Processing Hardware Memcpy from BRAM to 2 Accelerator is too fast!! Hardware Memcpy from 1 to BRAM Processing Hardware Memcpy from BRAM to 1

9 Power and performance analysis Valid voltages range from 1 volt to 0.72 volt and frequencies range from 170 MHz to 68 Mhz. Most energy efficient point with negligible impact in performance occurs at 0.72 volts and 68 MHz. Running the FPGA at nominal 1 v and 68 MHz results in 70-85% higher energy.

10 Energy analysis Processor and FPGA fabric energy analysis FPGA fabric energy analysis

11 Combining voltage, frequency and logic scaling in AVLS. Configuration 1 Configuration 2 Configuration 3 A configurable core can change the effective capacitance affecting both dynamic and static power : Power = α.c.v 2.f+g1.V 3 Hardware configurations with different levels of complexity easy to obtain with highlevel synthesis. Possible at run-time in modern FPGAs that enable partial dynamic reconfiguration.

12 Next steps Case study based on fusion application shows that adaptive voltage scaling with in-situ detectors can significantly improve performance or reduced energy by computing to the limit of correctness. Can we go beyond this limit and how fast can we find these points? AVLS extends AVS by adjusting the logic (i.e. capacitance) of the design at run-time: big/slow cores or small/fast cores? Application dependent. The AVLS concept could be controllable in a energy-aware run-time system under an OpenCL framework. The in-situ detector idea could be extended (by the manufacturer) to the hardened processor and memory subsystem.