Midterm Exam. Solutions

Transcription

1 Midterm Exam Solutions

2 Problem 1 List at least 3 advantages of implementing selected portions of a complex design in software

3 Software vs. Hardware Trade-offs Improve Performance Improve Energy Efficiency Reduce Power Density Manage Design Complexity Reduce Design Cost Stick to Design Schedule Handle Deep Submicron Implement more in Hardware Implement more in Software Source: A Practical Introduction to Hardware/Software Codesign

4 Problem 2 What are the primary advantages of Zynq All Programmable SoC over a traditional FPGA, such as Virtex 7, with a soft microprocessor core, such as MicroBlaze?

5 Clock frequency Area Power

6 Problem 3 Explain the term differentiation, and describe how Zynq can be used to accomplish a high-level of differentiation

7 In economics and marketing, product differentiation (or simply differentiation) is the process of distinguishing a product or service from others, to make it more attractive to a particular target market. This involves differentiating it from competitors' products as well as a firm's own products.

8 Choice Among Various Implementation Platforms Source: Xcell Journal, no. 88, Q3 2014

9 Problem 4 List at least 4 major advantages of Vivado over ISE

10 Vivado Design Suite scalable data model, supporting designs with up to 100 million ASIC gate equivalents (GEs) based on industry standards, such as AMBA AXI4 interconnect IP-XACT IP packaging metadata Tool Command Language (Tcl) Synopsys Design Constraints (SDC)

11 Productivity Gains Synthesis tool 3x faster than Xilinx XST Substantial improvement in runtime and maximum design size compared to Xilinx ISE Vivado Simulator 3x faster than Isim Much better visibility into key design metrics, such as timing, power, resource utilization, and routing congestion much earlier during the design process Estimates becomes progressively more accurate

12 Multidimensional Analytical Placer ISE: One-dimensional, timing-driven place-and-route algorithms Simulated annealing algorithms that determine randomly where the tool should place logic cells Does adequate job for FPGAs below 1 million GEs Vivado: Modern multidimensional analytic placement algorithm Deterministically finds a solution that primarily minimizes: timing, congestion, and wire length Better results, fewer iterations Efficient up to 100 million GEs

13 Hierachical Chip Planning & Advantages of Standards ability to partition the design for processing by synthesis, implementation and verification divide-and-conquer team approach to big projects design preservation feature enabling repeatable timing results access to state of the art third-party EDA tools for tasks such as constraint generation formal verification static timing analysis

14 Power Optimization and Analysis capable of analyzing design logic and removing unnecessary switching activity advanced clock gating techniques up to 30% reduction in dynamic power power estimates at every stage of the design flow

15 IP Packager, Integrator, and Extensible IP Catalog any part of the design (including the entire design) can be turned into a reusable core at any level of the design flow: RTL netlist placed netlist placed-and-routed netlist IP-XACT descriptions easy to integrate into future designs IP Packager specifies the IP data using XML file Extensible IP Catalog allows users to build their own standard repositories from IP they ve created, licensed from Xilinx, or licensed from third-party vendors

16 Vivado HLS High Level Language C, C++, System C Vivado HLS Hardware Description Language VHDL or Verilog

17 Problem 5 List 4 families of Xilinx devices supported by both Vivado and ISE

18 Support for Xilinx Families 90 nm Spartan-3, Virtex-4 65 nm Virtex-5 ISE 45 nm Spartan-6 40 nm Virtex-6 28 nm Artix-7, Kintex-7, Virtex-7, Zynq 7000 Vivado Future families

19 Problem 6 List 4 families of Xilinx devices supported by both Vivado and ISE

20 Problem 5 How many different types of interrupts can be generated by the AXI GPIO core?

21 GPIO Core Source: LogiCORE IP AXI GPIO: Product Specification

22 Interrupt Status Registers, IP ISR Status Status Source: LogiCORE IP AXI GPIO: Product Specification

23 Problem 7 Explain the ways of minimizing the area of the GPIO core, shown conceptually in the diagram below

24 AXI GPIO Resource Utilization and Maximum Clock Frequency Source: LogiCORE IP AXI GPIO: Product Specification

25 Problem 8 Explain the role and functionality of GPIO_TRI registers, shown in the diagram above

26 Problem 9 What are the primary limitations of the Accelerator Coherency Port (ACP) of Zynq, which go against the idea of full coherency?

27 Accelerator Coherency Port (ACP) Summary ACP allows limited support for Hardware Coherency Allows a PL accelerator to access cache of the Cortex-A9 processors PL has access through the same path as CPUs including caches, OCM, DDR, and peripherals Access is low latency (assuming data is in processor cache) no switches in path ACP does not allow full coherency PL is not notified of changes in processor caches Use write to PL register for synchronization

28 Problem 10 Explain the operation of the PWM mode of the AXI Timer (shown in the diagram below)

29 Pulse Width Modulation (PWM) Mode Two timer/counters are used as a pair to produce an output signal (PWM0) with a specified frequency and duty factor Timer 0 sets the period Timer 1 sets the high time for the PWM0 output Can be used to generate Periodical signals with varying period and duty cycle

30 Problem 11 Which mode of AXI Timer can be used to measure interval between two external events, such as two consecutive pushes of a button connected to the pins of PL?

31 Capture Mode The counter can be configured as an up or down counter The value of the counter is stored in the load register when the external capture signal is asserted The TINT flag is also set on detection of the capture event The Auto Reload/Hold (ARHT) bit controls whether the capture value is overwritten with a new capture value before the previous TINT flag is cleared Can be used to measure Widths of non-periodical signals Periods of periodical signals Intervals between edges of two different signals, etc.

32 Problem 12 Explain the difference between AXI Interconnect and AXI Interface

33 Interconnect vs. Interface

34 Interface AXI Interfaces and Interconnects A point-to-point connection for passing data, addresses, and hand-shaking signals between master and slave clients within the system Interconnect A switch which manages and directs traffic between attached AXI interfaces Source: The Zynq Book

35 Problem 13 Explain the primary differences between AXI Full and AXI Stream Interfaces

36 AXI Memory-Mapped vs. AXI Stream Source: M.S. Sadri, Zynq Training

37 Summary of AXI Full and AXI Lite Interfaces Source: Building Zynq Accelerators with Vivado HLS, FPL 2013 Tutorial

38 Summary of AXI Stream Interface Source: Building Zynq Accelerators with Vivado HLS, FPL 2013 Tutorial

39 Problem 14 Provide the names of at least two System-on-Chip Bus Standards competing with AMBA AXI4 standards

40 Competing System-on-Chip Bus Standards Bus Developed by High- Performance Shared Bus Peripheral Shared Bus AMBA v3 ARM AHB APB Point-to-Point Bus AMBA v4 ARM AXI4 AXI4-Lite AXI4-Stream Coreconnect IBM PLB OPB Wishbone SiliCore Corp. Crossbar Topology Shared Topology Point to Point Topology Avalon Altera Avalon-MM Avalon-MM Avalon-ST AMBA: Advanced Microcontroller Bus Architecture AXI: Advanced extensible Interface AHB: AMBA High-speed Bus APB: AMBA Peripheral Bus PLB: Processor Local Bus OPB: On-chip Peripheral Bus MM: Memory Mapped ST: Streaming Source: A Practical Introduction to Hardware/Software Codesign

41 Problem 15 Explain the need for the highlighted operations in case of the DMA-based communication between an ARM core and a hardware accelerator using GP Ports between PS and PL. A. Write to Accelerator processor allocates buffer processor writes data into buffer processor flushes cache for buffer processor initiates DMA transfer B. Read from Accelerator processor allocates buffer processor initiates DMA transfer processor waits for DMA to complete processor invalidates cache for buffer processor reads data from buffer

42 Write to Accelerator without Cache Flushing ARM Core Cache HW Accelerator Main Memory (DDR or OCM)

43 Write to Accelerator with Cache Flushing ARM Core Cache HW Accelerator Main Memory (DDR or OCM)

44 Read from Accelerator without Invalidating Cache ARM Core Cache HW Accelerator Main Memory (DDR or OCM)

45 Read from Accelerator with Invalidating Cache ARM Core Cache HW Accelerator Main Memory (DDR or OCM)

46 Problem 16 Explain the meaning of each number in the following estimate of the maximum bandwidth supported by A. HP ports of Zynq: Maximum bandwidth = 4 * 64 bits * 150 MHz * 2 = 9.6 GByte/sec B. external DDR Maximum bandwidth = 1 * 32 bits * 2 * 533 MHz * 2 = 4.3 GByte/s

47 A. HP ports of Zynq: Maximum bandwidth = 4 * 64 bits * 150 MHz * 2 = 9.6 GByte/sec Bidirectional transfer PL clock frequency Data bus width for HP interfaces Number of HP interfaces

48 B. external DDR Maximum bandwidth = 1 * 32 bits * 2 * 533 MHz * 2 = 4.3 GByte/s Bidirectional transfer Maximum clock rate (clock frequency) of DDR3 Double data rate (using both clk edges) Data bus width for DRAM interface Number of DRAM interfaces

49 Problem 17 What operation starts a Scatter Gather DMA Transfer when using AXI DMA?

50 Scatter Gather DMA Transfer Programming Sequence for MM2S channel (1) 1. Write the address of the starting descriptor to the Current Descriptor register 2. Start the MM2S channel running by setting the run/stop bit to 1, MM2S_DMACR.RS = If desired, enable interrupts by writing a 1 to MM2S_DMACR.IOC_IrqEn and MM2S_DMACR.Err_IrqEn. 4. Write a valid address to the Tail Descriptor register. Writing to the Tail Descriptor register triggers the DMA to start fetching the descriptors from the memory.

51 Simple DMA Transfer Programming Sequence for S2MM channel (1) 1. Write the address of the starting descriptor to the Current Descriptor register 2. Start the S2MM channel running by setting the run/stop bit to 1, S2MM_DMACR.RS = If desired, enable interrupts by by writing a 1 to S2MM_DMACR.IOC_IrqEn and S2MM_DMACR.Err_IrqEn. 4. Write a valid address to the Tail Descriptor register. Writing to the Tail Descriptor register triggers the DMA to start fetching the descriptors from the memory.

52 Chain of Buffer Descriptors (BDs)

53 Scatter Gather DMA Mode Source: Symbian OS Internals/13. Peripheral Support

54 Problem 18 What is the primary advantage of using a Scatter-Gather DMA Transfer rather than a Simple DMA transfer?

55 Scatter Gather DMA Mode Source: Symbian OS Internals/13. Peripheral Support

56 Problem 19 Based on the table below calculate the latency in nanoseconds for communication between: A. DMA and DDR, using HP interface B. ARM and internal memory of AXI Slave located in PL, using GP interface L1 Cache L2 Cache DDR OCM IOP Slave M_AXI_GP0 CPU Pipeline Peripheral Master S_AXI_ACP S_AXI_HP S_AXI_GP

57 AXI Interconnects and Interfaces ACP - Accelerator Coherency Port SCU - Snoop Control Unit Source: The Zynq Book

58 Processing system CPU at 667 MHz (650 MHz on Zybo board) DDR at 533 MHz Programmable logic is running at 150 MHz Latency in terms of CPU clock cycles S_AXI_HP at 76 CPU cycles is 17 cycles for the PL (114 ns) CPU Clock Period = 1 / CPU Clock Frequency = 1.5 ns A. 76 * 1.5 ns = 114 ns B. 86 * 1.5 ns = 129 ns

59 Problem 20 Provide any missing fragments of the VHDL code describing Xilinx BRAM in the WRITE_FIRST mode, illustrated in the diagram below

60 Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 60

61 Problem 21 Explain the difference between Simple Dual Port RAM and True Dual Port RAM

62 Block RAM Simple Dual Port (SDP) = one port for read, one port for write (write_a-read_b, read_a_write_b) True Dual Port (TDP) = both ports can be used for read or write (read_a-read_b, read_a-write_b, write_a-read_b, write_a-write_b) 62

63 Problem 22 List at least 3 primary differences between distributed RAM and Block RAM in Zynq

64 1. Location and basic building blocks 2. Distributed RAM has asynchronous output Block RAM has synchronous output. 3. Dual Port Distributed RAM requires twice as many resources (MLUTs) Dual Port Block RAM requires the same number of resources as a Single-Port Block RAM 4. Distributes Dual Port RAM does not allow two writes, only one read and one write. Dual Port Block RAM does not have this restriction

65 Location of Distributed RAM Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 65

66 Location of Block RAMs Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 66

67 Single-port 64 x 1-bit RAM 67

68 Problem 23 Determine the number of address bits, data bits, and parity bits in PORTA of a 36k BRAM configured as True Dual Port RAM, with 2048 memory locations

69 2048 = 2 11 => 11 address bits 36k / 2k = 18 => 16 data bits + 2 parity bits

70 Problem 24 Determine the number of MLUTs necessary to implement 128x8 Dual Port RAM

71 2 LUTs for 64x1 Dual-Port RAM 128 x 8 / 64 x 1 = * 2 = 32 LUTs needed

72 Problem 25 Supplement the attached timing diagrams with the values of dout for A. Standard FIFO B. B. First-Word Fall-Through FIFO

73 Operation of the Standard FIFO A B C D 73

74 Operation of the First-Word Fall-Through FIFO 74