Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles

Transcription

1 Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles Zhiyi Yu, Bevan Baas VLSI Computation Lab, ECE Department University of California, Davis, USA

2 Outline Introduction Timing issues Scalability issues A design example

3 Tile-based Chip Multiprocessors and GALS Clocking Style Chip multiprocessors High performance due to parallel computing Potential high energy efficiency since high performance may allow reducing clock and voltage Tile-based architecture Highly scalable Globally Asynchronous Locally Synchronous Simplified clock tree design High energy efficiency from adaptive clock/voltage scaling for each module

4 Tile-based GALS Chip Multiprocessors Globally synchronous vs. GALS Tile-based GALS chip multiprocessors have nearly perfect scalability

5 Hierarchical Physical Design Flow Three steps Oscillator Single processor Entire chip Chip array is assembled by a simple tiling of processors HDL (Verilog or VHDL) OSC Single processor Entire chip Synthesis Floorplan Placement Clock tree insertion In-place optimization Final Layout (ready for fabrication) Route Layout edit

6 The Challenges Timing issues Boundaries between clock domains Scalability issues The most important global signal (clock) is avoided But, clock might not be the only global signal P1 P2 clk1 clk2 programming, configuration P1 P2 P3

7 Outline Introduction Timing issues Scalability issues A design example

8 Two Methods to Cross the GALS Clock Domains Single transaction handshake Each data word is acknowledged before a subsequent transfer Coarse grain flow control Data words are transmitted without an individual acknowledgement

9 Overview of Timing Issues Proc. A s clk domain Proc. B s clk domain Clk A A B clock clk tree Clk B B C clock A B signals B C signals FIFO Proc. A A B signals FIFO Proc. B B C signals Signal categories between processor A and B A to B clock, synchronizing the source signals A to B signals, data and other signals such as valid B to A signals, such as ready or hold signals Each processor contains two clock domains

10 Two Clock Domains within One Processor Use dual-clock FIFO to handle the unrelated read and write clock within one processor Multiple Flip-flops are inserted at the clock domain boundary as a configurable synchronizer

11 Inter-processor Timing Issues --- Three Communication Methods send data send valid send clk Relative comm. power method (a) method (b) method (c) (a): sends clock only when there is valid data (b): sends clock one cycle earlier and one cycle later than the valid data (c): always sends clock

12 Timing Waveform of the Inter-processor Communication Send clk Send data Dclk Rec. clk Rec. data DLY Rec. data Ddata timing violation DDLY sample time, no timing violation

13 Circuitry for Inter-processor Communication Ddata_A Ddata_w Ddata_B clk_upstrm clk tree clk_dnstrm write signal (data,valid) Output logic DLY FIFO_full_in out in input logic FIFO_full_out DLY FIFO SRAM Proc. A Proc. B Dclk_A Dclk_w Dclk_B Insert configurable DLY logic at the path of data Compensate the additional clock tree delay and avoid the timing violation

14 Inter-chip Communication DA1 DA2 D1 2 DB2 DB1 data clk Chip 1 Chip 2 Inter-chip communication shares similar features with inter-processor communication The path is longer and the timing is more complex Output processor might need low speed clock Destination processor can operate at full speed

15 Outline Introduction Timing issues Scalability issues A design example

16 Special Signals Besides Clock Avoiding designing a global clock enhances scalability, but there are some other signals that must be addressed to maintain high scalability Various global signals such as configuration and test signals Power distribution Processor IO pins Key idea: avoid or isolate all global signals if possible, so multiple processors can be directly tiled without further changes

17 Clocking and Buffering of There are unavoidable global signals such as configure and test Three options: Pipeline these signals Asynchronous interconnect Use a low speed clock, and buffer signals in each processor Global Signals

18 Complete Power Distribution for Each Processor Metal 2 Metal 2 Metal 2 Metal 2 Metal5 Metal1 OSC grid not connected to main grid OSC power ring OSC power grid Metal6 Tile boundary Metal6 Metal6 Core boundary Metal6

19 Position of IO Pins Position of IO pins is important since they must connect to other processors Align IO pins with each other so that connecting wires are very short

20 Outline Introduction Timing issues Scalability issues A design example

21 An Asynchronous Array of simple Processors (AsAP) Single-chip tile-based 6 x 6 GALS multiprocessor Simple architecture & small mems. for each processor Nearest neighbor interconnect between processors Targets computationally intensive DSP apps FIFO 0 FIFO 1 CPU OSC Output

22 Back-end Design Flow Standard cell based design flow was used RTL coding Synthesis Placement & Routing Intensive verification were used throughout the design process Gate level analysis Circuit level simulation DRC/LVS Formal verification HDL (Verilog or VHDL) Synthesized verilog Final layout (ready for fabrication) Synthesis P & R Layout edit Design procedure Final verilog timing Formal Verification Gate level dynamic & static timing analysis DRC, LVS Spice netlist Spice level Simulation Verification procedure

23 Chip Micrograph Technology: TSMC 0.18 µm Max speed: V Area: 1 Proc 0.66 mm² Chip 32.1 mm² single processor Power (1 1.8V, 475 MHz): Typical application 32 mw Typical 100% active 84 mw Power(1 0.9V, 116 MHz): Typical application 2.4 mw

24 Summary GALS tile-based chip multiprocessor is an attractive architecture High performance, energy efficient, and highly scalable Timing issues Multiple clock domains in one single processor Inter-processor communication Inter-chip communication Scalability issues Global signals Power distribution IO pins

25 Funding Acknowledgments Intel Corporation UC Micro NSF Grant No UCD Faculty Research Grant Special Thanks E. Work, D. Truong, W. Cheng, T. Jacobson, T. Mohsenin, R. Krishinamurthy, M. Anders, and S. Mathew MOSIS Artisan