VLSI Education in India : Towards Excellence, Numbers and Relevance

Transcription

1 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Presenter : Chandra Shekhar IC Design Group CEERI Pilani (Rajasthan) Phone : FAX :

2 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Eduation and R&D : Indian Mile-Stones Start of VLSI Eduation in India with the publiation of the path-breaking book, Introdution to VLSI System Design by Mead and Conway in 1980, and the introdution of VLSI Design ourses based on it by some IITs. Adoption of the book s methodology by TIFR and CEERI for their design R&D work. Conurrently, MOS tehnology development related R&D work was being pursued at TIFR, CEERI and IITs. CEERI, PilaniIC Design Group 1

3 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Setting up of SCL and the VLSI Task Fore by Government of India. Big hopes! Big proposals and investment reommendations! Only realisti followups First ommerial interative layout design system (among aademi and R&D institutes) installed at CEERI s Delhi Centre under UNDP support An Applion System. Mid 1980s Evolution of more foused integrated eletronis and iruits oriented ME/MTeh degree programmes at IITs. CEERI, PilaniIC Design Group 2

4 VLSI Eduation in India : Towards Exellene, Numbers and Relevane First multinational ompany, TI, sets up its R&D Centre in India (for EDA tool development and software verifiation) First real appliation of Mead-Conway methodology to design a full ustom LSI proessor the PWM proessor for variable frequeny AC drives at CEERI, Pilani together with UCL, Belgium (under UNDP support). CEERI, PilaniIC Design Group 3

5 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Setting up of Aademi and R&D VLSI Design Centres at IITs and CEERI under a major initiative of the then Department of Eletronis (DoE), Government of India. Aademi Centres were equipped with Sun workstations and VTI tools (an integrated tool-set for full-ustom and semi-ustom logi, iruit and layout design and verifiation) and the indigenous semi-ustom design tool Vinyas developed by ITI that ran on a partiular brand of PC (the OMC PC-286 and PC-386). Along side these aademi-r&d entres, 10 industrial VLSI Design Centres were also set up by DoE 5 under the harge of SCL and 5 under the harge of ITI. CEERI, PilaniIC Design Group 4

6 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Development of PLA-based FSM ompiler at CEERI, Pilani. Development of a high-level synthesis tool under the Rahana projet at IIT- Delhi. Start of VLSI Design Workshop and International Conferene. Early 1990s Suessful hip design-developments by aademi-r&d design entres : CEERI (for C-DoT) using VTI tools and VTI foundry. IIT-Kharagpur and Jadavpur University using Vinyas tools and ITI foundry. CEERI, PilaniIC Design Group 5

7 VLSI Eduation in India : Towards Exellene, Numbers and Relevane 1994 Introdution of the Indian aademia and R&D adoption of in modeling and simulation of a miro-proessor design by CEERI, Pilani. for 1997 Start of the first industry-sponsored MTeh programme VLSI Design, Tools and Tehnologies (VDTT) programme at IIT-Delhi sponsored by Philips and o-sponsored by a number of other industries. Subsequently, TCS has supported a MTeh degree programme at IIT-Bombay. CEERI, PilaniIC Design Group 6

8 VLSI Eduation in India : Towards Exellene, Numbers and Relevane 1998 onwards Major government initiative in VLSI eduation via DoE/MIT projet, Speial Manpower Development for VLSI Design and Related Software (SMDP), based on industrial and aademi inputs for the 9 plan. The projet has 7 Resoure Centres (RCs) and 12 Partiipating Institutes (PIs). RCs : IIT-Bombay, IIT-Delhi, IIT-Kanpur, IIT-Kharagpur, IIT-Madras, IIS-Bangalore and CEERI-Pilani. PIs : NITs at Warangal, Surathkal, Rourkela, Nagpur, Jaipur; IIT-Roorkee, IT-BHU, TIET-Patiala, PSGCT-Coimbatore, BEC-Howrah, SGSITS-Indore and Jadavpur University, Kolkata. CEERI, PilaniIC Design Group 7

9 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Ativities Under SMDP Furnishing of labs with Books, Workstations and PCs. Provision of CAD tools : Cadene, Synopsys, Model Teh, Tanner, Xilinx, Saber. 16 different Instrution Enhanement Programmes (IEP) of 2-3 weeks duration by RCs for the faulty members of PIs and RCs. Development of Learning Material (LM) on 25 different VLSI related subjets inluding 8 Laboratory Learning Materials. CEERI, PilaniIC Design Group 8

10 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Objetives of SMDP To start and strengthen ME/MTeh (VLSI Design / Miroeletronis) programmes at PIs to generate suh speialized graduate manpower annually. These are alled Type-II manpower. To expose the ME/MTeh students of other eletronis disiplines (ommuniations, ontrol,... ) to at least two relevant VLSI ourses. Manpower so trained is termed Type-III manpower. To expose under-graduate (BE/BTeh) students of EE/ECE/CS to two basi VLSI design ourses. This is Type-IV manpower. To promote PhD in Miroeletronis, alled Type-I manpower. CEERI, PilaniIC Design Group 9

11 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Corporate Initiatives in VLSI Eduation More than 10 publi and private setor orporates are involved in providing 4-6 months diplomas in VLSI Design. VLSI Design Industry : Indian Mile-Stones 1989 TI starts IC design and library related work. Arus and SASI initiate VLSI design related operations. EDA tool vendors set up support offies onwards Many MNCs start aptive design entres. EDA tools ompanies start software development entres. Many IC/VLSI design servies ompanies start operations. CEERI, PilaniIC Design Group 10

12 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Current Aademi Status Institutes offering ME/MTeh degree in VLSI/Miroeletronis disipline are the 6 (IITs and IIS) + 10 (NITs and Other) Institutes. Total Core Faulty Pool Size : Graduating Type-II Manpower/year : Graduating Type-III Manpower/year : Graduating Type-IV Manpower/year : 1,000-1,200 Graduating Type-I Manpower/year : 8-12 CEERI, PilaniIC Design Group 11

13 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Future Perspetive TCS+IIT-Bombay Report has projeted a need for about 4,000 ME/MTeh per year in VLSI/Embedded System Design. Requirements for generating 1,000 ME/MTeh per year : Required number of institutes : Required Faulty Pool size : VLSI Lab. Set-up : Rs Crore Books, Journals,... : Rs Crore Sholarships/Self-finane : For 2,000 Students CEERI, PilaniIC Design Group 12

14 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Bottle-neks Faulty pool size and its growth from the urrent level of to desired level of over the next 3 years. ME/MTeh thesis supervision. Funding of tools for deployment in numbers. Silion aess (tehnial and finanial support). CEERI, PilaniIC Design Group 13

15 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Possible Solutions Use of tehnology (dediated multimedia links via Internet / TV) for live broadasts of letures to partially alleviate the faulty short-fall in the immediate future as vigorous faulty-development proeeds side-by-side. Eletroni availability of leture/learning/ourse materials. Industry to pith-in with their senior engineer / projet leader level manpower as guest faulty (out of onvition and with full-support of their top-level management). Industry (private and publi-setor) and government R&D entres (DRDO, ISRO, CSIR, DAE) to very signifiantly inrease their in-take of ME/MTeh thesis students. CEERI, PilaniIC Design Group 14

16 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Problems Faed by Aademi Labs Course Labs Costs assoiated with the deployment of Hardware-Software in large numbers. Time needed to get started with the tools. Insuffiient tehnial support. Suggestions Use publi-domain / heaper / simpler ommerial tools. Selet senior students (with aptitude) as lab instrutors. They are better handson as ompared to senior faulty. They also set up a relaying mehanism from bath-to-bath. CEERI, PilaniIC Design Group 15

17 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Problems Faed by Aademi Labs Projet Labs Problems of installation, ommissioning, periodi updating and tehnial support for professionally-used tools. Long times involved in taming the tool learning how to use the tool (or the design environment and flows) and its features effetively to express one s design onepts and proeed with the design. Maintenane and upkeep of hardware items. Infrastruture support problems (UPS, Air-onditioning,... ). CEERI, PilaniIC Design Group 16

18 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Problems Faed by Aademi Labs Suggestions Appoint Laboratory Engineers whose defined job is to tame the tool (with oneptual inputs from the faulty). They should set up demos for the students on how to effetively use the tool and answer their speifi queries related to the tool-features and its apabilities. The lab engineers would also initially hand-hold the students in their tool usage. CEERI, PilaniIC Design Group 17

19 VLSI Eduation in India : Towards Exellene, Numbers and Relevane New Courses Needed RF IC Design and Test. Mixed-Signal Design and Test. VLSI-SoC System Arhiteting : that takes a unified view of logi design and its optimization aross hardware-software boundary to obtain the required speedpower-ost-design-time trade-offs offered by different approahes. VLSI (and SoC) Test and Testability : too little attention has been paid to it in aademis. Low-Power Design : iruit tehniques, logi styles, dynami voltage saling, dynami power management, low-power system and miro-arhiteting, lowpower odes and ompilers. CEERI, PilaniIC Design Group 18

20 VLSI Eduation in India : Towards Exellene, Numbers and Relevane New Courses Needed Memory Design and Memory Subsystem Design. Sensors, MEMS, Signal Conditioning and Interfae Ciruits. Signal Proessing and Arhitetures for Speeh / Audio / Video / Image / Multimedia Appliations. Courses on New and Evolving Standards in Different Appliations Areas (with a bearing on VLSI-SoC Arhitetures). CEERI, PilaniIC Design Group 19

21 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Strengthening of Researh Researh is the bedrok of any good graduate programme. Researh needs to be reognized as an essentiality for maintaining quality and relevane. New areas, new ourses, new topis, new examples, emphasis and larity are born out of researh only. Speial interest groups on partiular researh areas/topis that an tightly interat via the Net and meetings need to be formed to provide the neessary impetus and the supportive human environments required for good researh. This would help to set up researh ommunities among the aademi and R&D institutes. CEERI, PilaniIC Design Group 20

22 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Strengthening of Researh Need to network the researhers and their available knowledge for a larger tehnology demonstration projets for one or more appliation areas. This effort should also provide ase-study material for large system designs whih an be used as examples in post-graduate programmes. This would provide the graduate students a peek into large real-life projets thus bridging the gap between lass-room examples and industrial praties. CEERI, PilaniIC Design Group 21

23 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Challenges : Evolution of VLSI Design Senario Year Team Size Effort Nature of MDI* (At Peak) (Man-Years) Produt ASICs for 0.2 Glue Logi ASP, Chip-sets ASP, Analog, 0.7 Mixed-Signal RF, MEMS, 0.9 SoC Mix of all into 1.0 a Complex SoC * Multi-Disiplinarity Index CEERI, PilaniIC Design Group 22

24 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Challenges : Key Tehnologial Areas!Top-down Digital System Design and its Optimization for Silion Implementation.!CISC / RISC / DSP / Parallel / Appliation Speifi Instrution Set Proessors (ASIP).!Low-Power Ciruit Design, Logi Design, Tehnologial and Layout issues.!mixed Analog-Digital Design. CEERI, PilaniIC Design Group 23

25 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Challenges : Key Tehnologial Areas!Signal Integrity and other DSM issues.!rf IC Design and assoiated issues.!high-speed / High-Resolution / Low-Power A/D and D/A Arhitetures and Design.!Signal Proessing (Digital and Analog) and ASSP.!Design of Signal Conditioning and Interfae Ciruits for Sensors. CEERI, PilaniIC Design Group 24

26 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Challenges : Key Tehnologial Areas!Miro-system Design (MEMS/MEOS).!Testing and Testability.!Speeh Reognition and Synthesis.!Synthesis and Design Automation tehniques for all the above design areas. CEERI, PilaniIC Design Group 25

27 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Challenges : Appliation Areas!Teleommuniations and Networking.!High-end Computing.!Multimedia and Visualization.!Information Compression and Deompression.!Man-mahine Interfae.!Industrial Control and Robotis. CEERI, PilaniIC Design Group 26

28 VLSI Eduation in India : Towards Exellene, Numbers and Relevane VLSI Challenges : Appliation Areas!Automotives and Transportation.!Energy Management and Power Conversion.!Medial Eletronis and Implantable Devies.!Strategi Systems.!Environment Control and Pollution Monitoring.!Consumer Eletronis and Home Applianes. CEERI, PilaniIC Design Group 27

29 VLSI Eduation in India : Towards Exellene, Numbers and Relevane New VLSI Challenges Inter-disiplinary knowledge integration and harnessing. Wedding the knowledge of standards in the appliation areas with the VLSI- SoC arhitetural knowledge and the knowledge of key tehnial areas to realize ompetitive miroeletroni solutions. CEERI, PilaniIC Design Group 28

30 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Aademi Challenges in the Near Term Indian Books on VLSI Subjets : Text Books and Speialized Referene Books. Indian Aademi VLSI CAD Tools : Physial, Ciruit, Logi, RTL, HDL, Synthesis, Test,... Indian Aademi-R&D Proessors : CISC/RISC/DSP Cores, Compilers, IP Bloks,... CEERI, PilaniIC Design Group 29

31 VLSI Eduation in India : Towards Exellene, Numbers and Relevane Government s New Initiatives for VLSI Eduation Efforts are underway in the DIT/MCIT, Government of India to start a new projet for developing manpower in the area of VLSI Design and Embedded Systems. The summary of today s disussions an provide a valuable input towards this effort. CEERI, PilaniIC Design Group 30