ARCHITECTURE AND CAD FOR DEEP-SUBMICRON FPGAs

Transcription

1 ARCHITECTURE AND CAD FOR DEEP-SUBMICRON FPGAs

2 THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

3 ARCHITECTURE AND CAD FOR DEEP-SUBMICRON FPGAs Vaughn Betz Jonathan Rose Alexander Marquardt University of Toronto Springer Science+Business Media, LLC

4 Library of Congress Cataloging-in-Publication Data Betz, Vaughn. Architecture and CAD for deep-submicron FPGAs / Vaughn Betz, Jonathan Rose, Alexander Marquardt. p. cm. - (Kluwer international series in engineering and computer science ; SECS 497) Includes bibliographical references and index. ISBN ISBN (ebook) DOI / Field programmable gate arrays Design and construction Data processing. 2. Programmable array logic. 3. Computer-aided design. I. Rose, Jonathan. II. Marquardt, Alexander. III. Title. IV. Series. TK7895.G36B '5--dc CIP Third Printing Copyright 1999 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1999 Softcover reprint of the hardcover 1st edition 1999 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC. Printed on acid-free paper. This printing is a digital duplication of the original edition.

5 To Corinne, William, and Isabel, Betty and Frank Rose, Marie and Ron

6 Table of Contents CHAPTER 1 Introduction Overview of FPGAs FPGA Architectural Issues Approach and CAD Tools Book Organization Acknowledgments... 9 CHAPTER 2 Background and Previous Work... ~ FPGA Architecture...' FPGA Programming Technologies FPGA Logic Block Architecture FPGA Routing Architecture CAD for FPGAs Synthesis and Logic Block Packing Placement Routing Delay Modelling Timing Analysis Summary CHAPTER 3 CAD Tools: Packing and Placement Logic Block Packing Cluster-Based Logic Blocks Basic Logic Block Packing Algorithm: VPack Timing-Driven Logic Block Packing: T-VPack Cluster Seed and Attraction Function Computational Complexity vs. Frequency of Timing Analysis... 47

7 viii Table of Contents Result Quality oft-vpack vs. VPack Placement: VPR Overview of the VPR Placement Tool New Adaptive Annealing Schedule New Cost Function: Linear Congestion Incremental Net Bounding Box Updates Summary CHAPTER 4 Routing Tools and Routing Architecture Generation Position within the CAD flow Architecture Parameterization and Generation Architecture Parameterization The Routing-Resource Graph Automatic Architecture Generation from Parameters Routability-Driven Router Cost Functions and Routing Schedules Speed Enhancements Timing-Driven Router Superiority of Elmore Delay to the Linear Delay Model Directly Optimizing the Elmore Delay Net Routing Algorithm Complexity Dynamic Base Costs Routing Schedule Delay Extraction and Timing Analysis Router and Placement Algorithm Validation Routability-Driven Router and Placement Algorithm Experimental Results with Input-Pin Doglegs Experimental Results Without Input Pin Doglegs Timing-Driven Router Summary CHAPTER 5 Global Routing Architecture Motivation Experimental Methodology

8 Table of Contents Ix CAD Flow..., Area-Efficiency Metric Significant FPGA Architectural Details Experimental Results: Directionally-Biased Routing Results for Square Logic Block Arrays Results for Rectangular Logic Block Arrays Experimental Results: Non-Uniform Routing CenterlEdge Capacity Ratio Single Center Channel Channel Summary CHAPTER 6 Cluster-Based Logic Blocks Motivation Experimental Methodology CAD Flow Area Model Delay Model Architecture Evaluation Metric: Area-Delay Product FPGA Architectural Assumptions Basic Architecture Routing Architecture Effect of Cluster Size on the Physical Length of FPGA Routing Segments Sizing Routing Transistors to Compensate for Different Physical Segment Lengths Cluster Inputs Required vs. Cluster Size Flexibility of Logic Block to Routing Interconnect vs. Cluster Size Speed and Area-Efficiency vs. Cluster Size Discussion of Delay vs. Cluster Size Results Effect of Cluster Size on Compile Time Summary

9 x Table of Contents CHAPTER 7 Detailed Routing Architecture Motivation Experimental Methodology FPGA Architectural Assumptions CAD Flow Delay Model Accuracy Area Model Importance of a Detailed Area Model Experimental Philosophy Single Wire Length Architectures Switch Block Issues Best Single Wire Length Amount of Connectivity Between Logic Blocks and Channels Two Types of Wire Segment Architectures Tri-State Buffer Routing Switches Only Length 4 Buffered Wires Plus Pass-Transistor-Switched Wires Length 8 Buffered Wires Plus Pass-Transistor-Switched Wires Length 4 Pass-Transistor-Switched Wires Plus Buffered Wires Internal Population All Length 4 Buffered Wires Two-Wire-TypeArchitectures Wire Spacing for Speed Overall Architecture Comparison Summary..., CHAPTER 8 Conclusions and Future Work Summary and Contributions Future Work CAD Tool Enhancements Future FPGA Architecture Research APPENDIX A Graphic Visualization in VPR APPENDIX B FPGA Circuitry and Process Modeling B.l Transistor-Level Schematics and Assumptions

10 Table of Contents xi B.1.1 FPGA Routing Structures Gate Boosting Buffers Connection Block to Logic Block Input Pins B.1.2 Logic Block Structures B.2 Delay and RC-Equivalent Circuit Extraction APPENDIX C Sizing of Routing Transistors and Metal C.1 Sizing Pass Transistor Routing Switches C.2 Sizing Tri-State Buffer Routing Switches C.3 Tri-State Buffers in Output Pin Connection Blocks CA Metal Width and Spacing References Index