FLASH MEMORIES SPRINGER-SCIENCE+BUSINESS MEDIA, LLC. Paulo Cappelletti. Carla Golla. PieroOlivo. Enrico Zanoni

Transcription

1 FLASH MEMORIES

2 FLASH MEMORIES By Paulo Cappelletti Carla Golla PieroOlivo Enrico Zanoni SPRINGER-SCIENCE+BUSINESS MEDIA, LLC

3 Library of Congress Cataloging-in-Publication Data Flash memories 1 by Paulo Cappelletti... (et al.). p. cm Includes bibliographical references. ISBN ISBN ( ebook) DOI / Flash memories (computers) TK7895.M4F dc21 I. Cappelletti, Paulo CIP Copyright 1999 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers, New York in 1999 Softcover reprint ofthe hardcover 1st edition 1999 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher, Springer-Science+Business Media, LLC Printed on acid-free paper.

4 Contents 1 FLASH MEMORIES: AN OVERVIEW 1 P. OLIVO, E. Zanoni 1.1 Role of Non Volatile Memories in Microelectronic Systems and in Semiconductor Market Evolution of Non-volatile Memories The Floating Gate Device Charge Injection Mechanisms Erasable Programmable Read Only Memories The Floating gate Avalanche-injection MOS transistor (FAMOS) Cell The basic Erasable Programmable Read Only Memory (EPROM) Electrically Erasable Programmable Read Only Memories The FLOating gate Thin Oxide (FLOTOX) Memory Cell Textured Polysilicon Cells The EEPROM Architecture Ferroelectric Memories Flash Memories. The Basic ETOX Cell. Programming and Erasing Mechanisms Memory NOR Architecture and Related Issues The NAND Flash Mass Storage Concept Embedded Flash Memories The Future of Flash Memories Evolution of Flash Memory Technology Non Volatile Memories Market Development 29 References 33 2 THE INDUSTRY STANDARD FLASH MEMORY CELL 37 P. Pavan, R. Bez

5 vi FLASH MEMORIES 2.1 I ntrod uction 2.2 Basic Structu re 2.3 Operating Conditions Read Program Erase 2.4 Technology and Process Isolation Well and Channel Doping Cell Structu re Defi n ition I nterlevel Dielectrics I ntercon nections 24.6 Final Passivation 25 Yield and Reliability Retention Endurance Reading Disturbs Programming Disturbs Erasing Disturbs 2.6 Scaling Issues References 3 BINARY AND MULTILEVEL FLASH CELLS B. Eitan, A. Roy 3 1 Introduction to Flash Cell Design 3.2 Binary Flash Cells Figures of Merit Cell Design Complication Hierarchy from ROM to Flash Basis for Flash Cells/Array Classification Detailed Description of Flash Cells and Architectures Scaling and Conclusions 3.3 Multilevel Flash Cells Introduction to the Concept of Multilevel Flash Multilevel Programming Mechanisms Architectures for Multilevel Flash Memories Scaling and Trade-Offs for Multilevel References 4 PHYSICAL ASPECTS OF CELL OPERATION AND RELIABILITY L. Selnu, C. Fiegna 4.1 Introduction 4.2 Electronic Properties of Carriers and MOS Structures Electrons in Crystals Electrons as Classical Particles

6 Cont.ent.s vii Silicon Silicon Dioxide Silicon - Silicon Dioxide Interface Oxide and Interface Traps Fundamentals of Tunneling Phenomena Basic Concepts and the WKB Approximation Transmission Coefficient Tunneling Current Tunneling Phenomena in MOSFETs Fowler-Nordheim and Direct Tunneling Through Gate Oxides Modeling the Tunnel Current of MOS Structures Band-to-band and Trap-to-band Tunneling Modeling the Band-to-band and Trap-to-band Tunneling Current Fundamentals of Carrier Transport The Distribution Function The Boltzmann Transport Equation Scattering The Carrier Distribution in Thermal Equilibrium Carrier Distributions in Homogeneous Electric Fields The Effective Temperature Model Hot Carrier Effects in MOSFETs Carrier Heating in MOSFETs and Flash Cells MOSFET Design and Carrier Heating Simplified Models of Carrier Heating Average Energy Carrier Distribution Impact Ionization Substrate Current Hot Carrier Injection into Si Distribution Function Injection Probability Gate Current Channel Hot Electron Injection Drain Avalanche Hot Carrier Injection Secondary Generated Hot Electron Injection Substrate Hot Electron Injection Implications for Device Operation Hot Carrier Effects at Low Voltages Oxide Degradation due to High Field Stress Oxide Wear-out and SILC Stress Induced Leakage Currents (SILC) Oxide Breakdown Lifetime Evaluation Models SILC Lifetime Evaluation Model Breakdown Lifetime Evaluation Model Oxide and Interface Degradation due to Hot Carrier Injection Homogeneous Hot Carrier Degradation n-channel Devices 217

7 viii FLASH MEMORIES p-channel Devices Non-homogeneous Hot Carrier Degradation Lifetime Evaluation Models References MEMORY ARCHITECTURE AND RELATED ISSUES 241 M. BraT/chettl, G. Campardo, S. Commodaro, S. Ghezz!. A. Ghzlardelll, C. Golla, M. Maccarmne, I. Martznes, R. Micheloni, J. Mulattz, M. ZammattlO, S. Zanardi 5.1 Flash Architecture: General Overview Flash Architecture Scenario NOR Cell Operation and Array Organization Flash Memory User Interface Flash Memory Operations' Overview Read Path Building Blocks Description Program Path Building Blocks Description Erase Path Building Blocks Description Read Path: Decoding Predecoding Row Decoder Column Decoder Hierarchical Decoder Low Vee Problems Boost Concept: Continuous Boost and "One-shot" Bost A New Boost Approach: Miniboost 53 Read Path: Input and Output Buffers 53.1 Input Buffer Output Buffer Noise Issues High Voltage Tolerance 5.4 Read Path: Sensing Techniques Sensing Techniques: An Overview 542 Differential Sensing Technique Differential Sensing Technique with Offset Current Differential Semi-Parallel Sensing Technique Reading Speed-up Techniques From EPROM to Flash Reading Flash Memories with Depleted Bits Low Voltage Flash Read Reference Problems 5.5 Program Operation Circuitry Cell Programming Voltages: Optimum Choice Typical Program Path Drain Voltage Regulation: Principles and Basic Circuits Gate Voltage Regulation Fundamentals 5 6 Erase Operation Circuitry Double Supply Voltage Approach

8 Contents IX Source Erase Circuitry Slow Discharge of Critical Nodes Single Supply Voltage Approach Charge Pumping Voltage Regulators Source Switch 5.7 Control Logic and Embedded Algorithms Logic Architecture 57.2 Embedded Algorithms Seq uencer (Pseudo- M icrocontroller) Finite State Machine 5.73 Program Flow Erase Flow Erase Suspend - Erase Resume 576 Testability Issues 58 Redundancy and Error Correction Codes The Yield Static Redundancy Wafer Yield A Real Case Error Correction Codes 6 MULTILEVEL FLASH MEMORIES G. Torelli. M. Lanzom. A. Manstretla. B. Ricco 6 1 I ntrod uction The Multilevel Approach 61.2 Basic Issues for ML Storage 6.2 Array Architectures for Multilevel Flash Memories NOR Architecture with CHE Programming NOR Architecture with FN Programming NAND Architecture 6 3 Multilevel Sensing 63.1 Signal Production and Recognition Sensing Schemes 6.4 Multilevel Programming 64 1 Program-and-Verify Approaches Self-Controlled Approaches 6 5 Conclusions References 7 F~ASH MEMORY RELIABILITY P. Cappelletti. A. Modelli 7 1 I ntrod uction 7.2 Memory Array Vi Distributions and Tunnel Oxide "Defects" 7.3 Main Yield and Reliability Issues

9 x FLASH MEMORIES Over-Erasing Program Disturbs Read Disturb Program/Erase Endurance Data Retention Testing for Reliability Failure Modes Induced by Program/Erase Cycling Memory Cell Intrinsic Endurance The Behavior of Tail Bits Single Bit Failure Mechanisms The Erratic Erase Phenomenon Single Bit Data Loss after Program/Erase Cycling Gain Degradation Multilevel Storage Reliability Conclusion 439 References FLASH MEMORY TESTING G. Casagrande 8.1 Introduction 8.11 Impact of Testing on Product Cost 8.12 Impact on Product Life Cycle Objectives of Production Testing Testing Versus Quality and Reliability 8.2 Flash Testing Aspects Flash Functional Model Oxide Stress in a Flash Flash Testing Aspects Conceptual Test Flow 83 Flash Testability Tools Focus on Cell and Technology Direct Memory Access Vt Measurement Stress Modes Depletion/Low-Vt Test Focus on Test Productivity Focus on Design Flash Design Testability: an Example Fault Repairing Error Correction Redundancy Diagnosis and Repairing Testability Tools for Redundancy Production Testing DC Tests

10 Contents xi Functional Testing AC Read/Command Interface Erase/Program Performance; Endurance Reliability 8.6 Test Productivity Impact on Tester Structure Parallel Testing Final Test Parallel Testing at EWS 8.7 Product Characterization 8.8 Conclusions References 9 FLASH MEMORIES: MARKET, MARKETING AND ECONOMIC CHALLENGES 481 B. Beverina, P. Berge, with contnbutions by C. Kunkel, G. Moy, A. Damzano, R. Ferrara, A. Re 9.1 Introduction Market Segmentations Application Segments and Subsegments Technology, Performances and Applications Segment Dynamics Commodity or Non-Commodity? Customer/Supplier Relationship The Development of the Flash Market Flash Memory and the "Economy" Applications More in Detail Survey Flash in Mobile Phones and Terminals Flash in the BIOS Flash in Automotive Conclusions References 526