PERFORMANCE ANALYSIS OF REAL-TIME EMBEDDED SOFTWARE

Transcription

1 PERFORMANCE ANALYSIS OF REAL-TIME EMBEDDED SOFTWARE

2 PERFORMANCE ANALYSIS OF REAL-TIME EMBEDDED SOFTWARE Yau-Tsun Steven Li Monterey Design Systems, Inc. Sharad Malik Princeton University ~. " SPRINGER SCIENCE+BUSINESS MEDIA, LLC

3 ISBN DOI / ISBN (ebook) Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. Copyright 1999 by Springer Science+Business Media New York in 1999 Originally published by Kluwer Academic Publishers in 1999 Softcover reprint of the hardcover Ist edition 1999 AlI rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC Printed on acid-free paper.

4 Contents List of Figures List of Tables Preface Acknowledgments ix xiii xv xvii 1. INTRODUCTION 1.1 The Emergence of Embedded Systems 1.2 Performance Constraints of Embedded Systems Challenges in Designing Embedded Systems Research Goals Two Sub-Problems Summary Organization of this Book 8 2. RELATED WORK IN TIMING ANALYSIS FOR EMBEDDED SOFTWARE Introduction Program Path Analysis Program Restrictions Extreme Case Timing Analysis Microarchitecture Modeling Retargetability Issues Summary PROGRAM PATH ANALYSIS Introduction Problems with Program Path Analysis Execution Count Analysis Program Control Flow and Logical Flow 28

5 vi PERFORMANCE ANALYSIS OF REAL-TIME EMBEDDED SOFTWARE 3.5 Integer Linear Programming Formulation Structural Constraints Functionality Constraints Functionality Constraints versus IDL Solving ILP Problems Experimental Validation Chapter Conclusions MICROARCHITECTURE MODELING Introduction Overview Simple Microarchitectures Advanced Microarchitectures and Memory Systems Cache Modeling Cache Organization Instruction Cache Modeling Difficulty in Instruction Cache Modeling Previous Work ILP techniques Direct Mapped Instruction Cache Analysis Cost Function Linking with Program Path Analysis Cache Constraints Set Associative Instruction Cache Analysis States of a Cache Set Set Associative Cache Constraints Interprocedural Calls Data Cache Modeling Simulation-Based Analysis Pipeline Modeling Experiments Instruction Cache Analysis Data Cache Analysis Cache and Pipeline Analysis Comparison with Other Analysis Techniques Chapter Conclusions A RETARGETABLE TIMING ANALYSIS TOOL - CINDERELLA Introduction Issues in Timing Analysis Basic Information for Timing Analysis Extracting Control Flow and Path Information 107

6 Contents vii 5.3 Classification of Retargeting Information Reading and Decoding the Program Modeling the Hardware 5.4 Implementation of Retargetable Modules Object File Module Instruction Set Module Machine Module ILP Solver Module User Interface 5.5 Operations 5.6 Chapter Conclusions 6. CONCLUSIONS 6.1 Contributions Program Path Analysis Microarchitecture Modeling Implementation 6.2 Future Research Directions Appendices A-Practical Complexity of the I LP Problems References Index 145

7 List of Figures 1.1 Estimated bound must enclose actual bound, which in turn encloses simulation results A simple wait loop whose loop bound cannot be determined automatically A simple for loop whose loop bounds can be determined statically An example of MARS-C code Different parts of the code are sometimes related Exponential blowup of program paths Different parts of the code are sometimes related Factors affecting the values of basic block variables An example of the if -then-else statement and its control flow graph An example of the while loop statement and its CFG An example showing how function calls are represented Loop bounds for nested loops. Line numbers and basic block variables (Xi'S) are labeled beside the source code check_data example from Park's thesis An example showing how the path relationship between the caller and the callee function can be specified The functionality constraints for function check_data () are expanded into four functionality constraint sets. At least one of them must be satisfied. Note that Set 2 and Set 3 are null sets because of the contradicting values on variable X An example code fragment to illustrate how the functionality constraints will affect the performance of solving the ILP instance Accuracy of program path analysis. 47

8 x PERFORMANCE ANALYSIS OF REAL-TIME EMBEDDED SOFfWARE 4.1 The partitioning of a memory address for locating its position in the cache Organization of a 2-way set associative cache with 4 cache sets A simple cache conflicting problem. Two statements, line 4 and 6 (shown in italic font), conflict with each other An example showing how the I-blocks are constructed A general cache conflict graph containing two conflicting I-blocks Cache conflict graph for the conflicting I-blocks in cache set 0 of the example shown in Figure An example control flow graph with two conflicting I-blocks (B4. 1 and B7. 1) from two different loops. The italicized numbers shown on the left of the variables are the worst case solution returned by the ILP solver Cache conflict graphs of conflicting I-blocks (B4.1 and B7.d in Figure 4.7. The italicized numbers shown on the left of the variables are the worst case solution returned by the ILP solver A simple example showing how the cache state transition graph is constructed when there are three conflicting I-blocks Bl.l, B4. 1 and B An example code fragment showing how function calls are handled Integrating data cache modeling with the rest A four-stage pipeline implemented in the Intel i960kb processor Accuracy in 512, byte direct mapped instruction cache analysis Accuracy in 512, byte 2-way set associative instruction cache analysis Accuracy in 1, KB 2-way set associative instruction cache analysis Accuracy in modeling programs running on Intel's QT960 evaluation board Comparison of estimated WCETs Comparison of estimated BCETs A block diagram showing the structure of cinderella. The dark area represents the target independent code. 113

9 LIST OF FIGURES xi 5.2 Graphical user interface of cinderella. The Cinderella window shows estimated bounds (best case and worst case) of the program, its source code and the basic block variables. When the mouse pointer is at the variable, a pop-up window displays further information for that variable. The Cache Table window shows how the basic blocks are mapped to the cache sets. The Functionality Constraints window shows linear constraints representing loop bounds and additional path information. The Assembly Code window displays the assembly instructions and their addresses. This is handy for tracing code transformations done by compiler optimizations Dialog box for selecting the top level function for analysis Dialog box for selecting the machine that is compatible with the selected program Simplified C++ code showing how the cinderella core reads a basic block for constructing the control flow graphs Providing a loop bound Dialog box for adding functionality constraint A flow chart showing the operations of cinderella. The left hand side shows the user actions and the right hand side shows the corresponding operations that cinderella performs. 125

10 List of Tables 2.1 Comparison of various extreme case performance analysis techniques Transformation from IDL to functionality constraints Set of benchmark examples, their descriptions, source file line sizes and Intel i960kb binary code sizes Program path analysis results. The estimated bound and the calculated bound are in units of clock cycles Complexity of program path analysis for the benchmark programs Results for 512, byte direct mapped instruction cache with 16, byte line size Results for 512, byte 2-way set associative instruction cache with 16, byte line size Results for 1, KB 2-way set associative instruction cache with 16, byte line size Results for data cache modeling Results for modeling programs running on Intel QT960 evaluation board Comparison of different analysis techniques Code size of cinderella Functions provided by object file module Functions provided by instruction set module Functions provided by machine module. 119

11 Preface Embedded systems are characterized by the presence of processors running application specific software. Recent years have seen a large growth of such systems. This trend is projected to continue with the growth of systems on a chip. Many of these systems have strict performance and cost requirements. To design these systems, sophisticated timing analysis tools are needed to accurately determine the extreme case (best case and worst case) performance of the software components. Existing techniques for this analysis have one or more of the following limitations: they cannot model complicated programs, they cannot model advanced micro-architectural features of the processor, such as cache memories and pipelines, they cannot be easily retargeted for new hardware platforms. These limitations often result in loose estimation of the software performance. Hence, more powerful and expensive hardware is typically required in conservatively overdesigned systems to guarantee that the software component meets all timing deadlines. This drives up the cost of the system unnecessarily. In this monograph, a new timing analysis technique is proposed to overcome the above limitations. The technique determines the bounds on the extreme case (best case and worst case) execution time of a program when running on a given hardware system. It partitions the problem into two sub-problems: program path analysis and microarchitecture modeling. Program path analysis analyzes the structure of the program and determines the set of paths that results in the extreme case execution time. Microarchitecture modeling accurately models the timing properties of the hardware, including pipelined processors and caches, and determines the execution time of a known sequence of instructions. The technique transforms the problem into a set in-

12 xvi PERFORMANCE ANALYSIS OF REAL-TIME EMBEDDED SOFfWARE teger linear programming problems, for which the optimum solution is the estimated worst case or best case execution time of the program. The timing analysis technique has been implemented in a tool called cinderella, which features a retargetable backend so that new hardware platforms can be modeled with minimum programming effort. Currently, the Intel i960kb and the Motorola M68000 platforms have been implemented. Extensive experiments have been conducted to show that the tool is capable of analyzing large and complicated programs accurately.

13 Acknowledgments I would like to express my sincere appreciation to Professor Sharad Malik, my Ph. D. thesis advisor at Princeton University, for his guidance, support, and encouragement. lowe him my gratitude for giving me the opportunity to work on the challenging and rewarding research reported in this monograph. This work has benefited from many stimulating discussions with Professors Andrew Wolfe and Margaret Martonosi. I would also like to thank our editor Carl Harris for his patience and help in preparing this monograph. Most of all, I would like to thank Leona Chan, my brother, and my parents for the constant support and encouragement. Finally, the support of this work by the Office of Naval Research (grant NOO ) is gratefully acknowledged. Vau-Tsun Steven Li The final work on this manuscript was completed while I was on sabbatical leave from Princeton University, and a visiting professor at the Indian Institute of Technology, New Delhi. I would like to thank both institutions for making this possible. Sharad Malik