Network Processors. Douglas Comer. Computer Science Department Purdue University 250 N. University Street West Lafayette, IN

Transcription

1 Network Processors Douglas Comer Computer Science Department Purdue University 250 N. University Street West Lafayette, IN Copyright All rights reserved. This document may not be reproduced by any means without written consent of the author.

2 Topic And Scope The emerging field of network processors: devices that form the basis of the modern packet processing systems used in computer networks and the Internet. We will examine the motivation, architectures and technologies. Network Processors

3 List Of Topics Generations of network systems Emergence of network processors Network processor architectures Network Processors

4 List Of Topics Generations of network systems Emergence of network processors Network processor architectures Network Processors

5 Our Goal Construct a network system Individual hardware component that processes packets May contain processor(s) and software Operates at one or more layers of the protocol stack Accommodate Change of specification during construction Changes for next-generation product Network Processors

6 Example Network Systems Layer 2 Bridge, VLAN switch, DSL modem Layer 3 IP router Layer 4 NAT box, TCP splicer Layer 5 Firewall, web load balancer, softswitch Network Processors

7 Challenges Operate at wire speed without packet loss Manage state information efficiently (e.g., TCP flow) Support traffic in both directions Handle reordered packets IP fragments especially difficult May require storing packets Network Processors

8 First Generation Network Systems Traditional software-based router Packet processing in software Use conventional (minicomputer) hardware Single CPU Single shared memory I/O over a bus Network interface cards function like other I/O devices Network Processors

9 Protocol Processing In First Generation Network Systems NIC 1 Standard CPU NIC 2 framing & address recognition all other processing framing & address recognition General-purpose processor handles most tasks NIC handles layer 1 and basic layer 2 tasks Sufficient for low-speed networks Network Processors

10 Statement Of Hope (1990 version) If there is hope, it lies in faster CPUs. Network Processors

11 How Fast Is A Fast Network? Definition of fast data rate keeps changing 1960: 10 Kbps 1970: 1 Mbps 1980: 10 Mbps 1990: 100 Mbps 2000: 1000 Mbps (1 Gbps) 2003: 2400 Mbps (2.4 Gbps) Network Processors

12 How Fast Is A Fast Network? Definition of fast data rate keeps changing 1960: 10 Kbps 1970: 1 Mbps 1980: 10 Mbps 1990: 100 Mbps 2000: 1000 Mbps (1 Gbps) 2003: 2400 Mbps (2.4 Gbps) Soon: 10 Gbps??? Network Processors

13 The Importance Of Packet Rates 10 5 Kpps Kpps 10 3 Kpps 10 2 Kpps Kpps 10 0 Kpps 10Base-T 100Base-T OC-3 OC Base-T OC-48 OC-192 OC-768 Gray areas show rates for large packets Network Processors

14 Fundamental Question About Software-Based Network Systems Which is growing faster? Processing power Network data rates Network Processors

15 Growth Of Technologies 10,000 1, Gbps OC Mbps OC-12 Pent.-3GHz 100 Mbps Pent.-400 FDDI Pent Gbps OC Mbps Ethernet Network Processors

16 Second Generation Network Systems Concurrent with ATM development (early 1990s) Purpose: scale to speeds faster than single CPU capacity Decentralized architecture with multiple NICs to offload CPU Classification rather than demultiplexing High-speed interconnect (switching fabric) General-purpose processor only handles exceptions Network Processors

17 Protocol Processing In Second Generation Network Systems Interface 1 Standard CPU Interface 2 Layer 1 & 2 Class- Forward- Control And Exceptions Forward- Class- Layer 1 & 2 (framing) ification ing fast data path ing ification (framing) NIC handles most of layers 1-3 Fast data path (switching fabric) avoids CPU completely Network Processors

18 Packet Classification Alternative to demultiplexing Designed for higher speed Considers all layers at the same time Linear in number of fields Network Processors

19 Illustration Of Classification ETHERNET DEST. (0-1) ETHERNET DESTINATION (2-5) ETHERNET SOURCE (0-3) ETHERNET SOURCE (4-5) ETHERNET TYPE VERS HLEN SERVICE IP TOTAL LENGTH IP IDENT FLAGS FRAG. OFFSET IP TTL IP TYPE IP HDR. CHECKSUM IP SOURCE ADDRESS IP DESTINATION ADDRESS TCP SOURCE PORT TCP DESTINATION PORT TCP SEQUENCE TCP ACKNOWLEDGEMENT HLEN NOT USED CODE BITS TCP WINDOW TCP CHECKSUM TCP URGENT PTR Start Of TCP Data... Highlighted fields are used for classification of Web server traffic Network Processors

20 Switching Fabric Used inside a single network system Central interconnects for I/O ports (and possibly CPU) Can transfer unicast, multicast, and broadcast packets Typical architecture: synchronous bus Network Processors

21 Third Generation Design NIC contains ASIC hardware Embedded processor plus code in ROM NIC handles Packet forwarding Traffic policing Monitoring and statistics Network Processors

22 Protocol Processing In Third Generation Systems Interface 1 Standard CPU Interface 2 Layer 4 Other processing Layer 4 Layers 1 & 2 Embedded processor Layer 3 & class. ASIC Traffic Mgmt. (ASIC) fast data path Embedded Processor Layer 3 & class. ASIC Layers 1 & 2 Special-purpose ASICs handle lower layer functions Embedded (RISC) processor handles layer 4 CPU only handles low-demand processing Network Processors

23 Statement Of Hope (1995 version) If there is hope, it lies in ASIC designers. Network Processors

24 List Of Topics Generations of network systems Emergence of network processors Network processor architectures Network Processors

25 Problems With Third Generation Systems High cost Long time to market Difficult to simulate/test Require in-house expertise (ASIC designers) Expensive and time-consuming to change months for silicon respin Little reuse across products Limited reuse across versions Network Processors

26 Statement Of Hope (1999 version)??? If there is hope, it lies in ASIC designers. Network Processors

27 A Fourth Generation Goal: combine best features of first generation and third generation systems Flexibility of programmable processor High speed of ASICs Technology called network processors Network Processors

28 Definition Of A Network Processor A network processor is a special-purpose, programmable hardware device that combines the low cost and flexibility of a RISC processor with the speed and scalability of custom silicon (i.e., ASIC chips). Network processors are building blocks used to construct network systems. Network Processors

29 Network Processors: Potential Advantages Relatively low cost Straightforward hardware interface Facilities to access Memory Network interface devices Programmable Ability to scale to higher Data rates Packet rates Network Processors

30 Network Processors: Potential Advantages Relatively low cost Straightforward hardware interface Facilities to access Memory Network interface devices Programmable Ability to scale to higher Data rates Packet rates Network Processors

31 Statement Of Hope (2003 version) programmers! If there is hope, it lies in ASIC designers. Network Processors

32 Costs And Benefits Of Network Processors? ASIC Designs Increasing Performance Software On Conventional Processor? Network Processor Designs Increasing cost Currently more expensive than conventional processors Currently slower than ASICs Future trends still unclear Network Processors

33 List Of Topics Generations of network systems Emergence of network processors Network processor architectures Network Processors

34 What is known Network Processor Design Must partition packet processing into separate functions To achieve highest speed, must handle each function with separate hardware Still being researched Which functions to choose Which hardware building blocks to use How building blocks should be interconnected Network Processors

35 The Range Of Architecture Styles Embedded processor plus fixed coprocessors Embedded processor plus programmable I/O processors Parallel (number of processors scales to handle load) Pipeline processors Network Processors

36 Embedded Processor Architecture f(); g(); h() Single processor Handles all functions Passes packet on Known as run-to-completion Network Processors

37 Parallel Architecture coordination mechanism f(); g(); h() f(); g(); h(). f(); g(); h() Each processor handles 1/N of total load Network Processors

38 Pipeline Architecture f () g () h () Each processor handles one function Packet moves through pipeline Network Processors

39 Clock Rates Embedded processor runs at > wire speed Parallel processor runs at < wire speed Pipeline processor runs at wire speed Network Processors

40 Commercial Network Processors Emerge in late 1990s Become popular in early 2000s Exceed thirty vendors by 2003 Network Processors

41 Examples Chosen to Illustrate concepts Show broad categories Expose the variety Not necessarily best Not meant as an endorsement of specific vendors Show a snapshot as of 2003 Network Processors

42 Multi-Chip Pipeline (Agere) Brand name PayloadPlus Three individual chips Fast Pattern Processor (FPP) for classification Routing Switch Processor (RSP) for forwarding Agere System Interface (ASI) for traffic management and exceptions Note: second generation will use a single chip Network Processors

43 Multi-Chip Pipeline (Agere) (continued) Fast Pattern Processor ( FPP ) Routing Switch Processor ( RSP ) packets arrive configuration bus packets sent to fabric Agere System Interface ( ASI ) Network Processors

44 Architecture Of Agere s FPP Chip data buffer input framer data buffer controller output interface block buffers and context memory program memory pattern engine checksum / CRC engine control memory queue engine ALU conf. bus interface functional bus interface Network Processors

45 Augmented RISC (Alchemy) Based on MIPS-32 CPU Five-stage pipeline Augmented for packet processing Instructions (e.g. multiply-and-accumulate) Memory cache I/O interfaces Network Processors

46 Alchemy Architecture to SDRAM SDRAM controller fast IrDA SRAM bus MIPS-32 embed. proc. MAC instruct. cache bus unit data cache EJTAG DMA controller Ethernet MAC LCD controller SRAM controller RTC (2) power management SSI (2) AC 97 controller USB-Host contr. USB-Device contr. interrupt controller GPIO I 2 S Serial line UART (2) Network Processors

47 Parallel Embedded Processors Plus Coprocessors (AMCC) One to six np core processors Various engines Packet metering Packet transform Packet policy Network Processors

48 AMCC Architecture external search interface external memory interface host interface policy engine metering engine memory access unit six np cores onboard memory input packet transform engine output control iface debug port inter mod. test iface Network Processors

49 Pipeline Of Homogeneous Processors (Cisco) Parallel express Forwarding (PXF) Arranged in parallel pipelines Packet flows through one pipeline Each processor in pipeline dedicated to one task Network Processors

50 Cisco Architecture input MAC classify Accounting & ICMP FIB & Netflow MPLS classify Access Control CAR MLPPP WRED output Network Processors

51 Configurable Instruction Set Processors (Cognigine) Up to sixteen parallel processors Connected in a pipeline Processor called Reconfigurable Communication Unit (RCU) Interconnected by Routing Switch Fabric (RSF) Instruction set determined by loadable dictionary Network Processors

52 Cognigine Architecture routing switch fabric connector pointer file dictionary packet buffers registers & scratch memory data memory instr. cache source route source route source route source route addr. calc. execut. unit execut. unit execut. unit execut. unit dict. decode pipeline ctl. Network Processors

53 Four processor types Pipeline Of Parallel Heterogeneous Processors (EZchip) Each type optimized for specific task Network Processors

54 EZchip Architecture TOPparse TOPsearch TOPresolve TOPmodify.... memory memory memory memory Network Processors

55 EZchip Processor Types Processor Type TOPparse TOPsearch TOPresolve TOPmodify Optimized For Header field extraction and classification Table lookup Queue management and forwarding Packet header and content modification Network Processors

56 Extensive And Diverse Processors (IBM) Multiple processor types Extensive use of parallelism Separate ingress and egress processing paths Multiple onboard data stores Model is NP4GS3 Network Processors

57 IBM NP4GS3 Architecture to switching fabric PCI bus external DRAM and SRAM from switching fabric ingress data store ingress switch interface internal SRAM egress switch interface egress data store SRAM for ingress data Embedded Processor Complex (EPC) traffic manag. and sched. ingress physical MAC multiplexor egress physical MAC multiplexor packets from physical devices packets to physical devices egress data store Network Processors

58 IBM s Embedded Processor Complex to onboard memory to external memory H 0 H 1 H 2 H 3 H 4 S D 0 D 1 D 2 D 3 D 4 D 5 D 6 control memory arbiter ingress queue completion unit egress queue interrupts exceptions debug & inter. hardware regs. inter. bus control ingress data store ingress data iface programmable protocol processors (16 picoengines) embed. PowerPC egress data iface... PCI bus egress data store ingress data store instr. memory classifier assist bus arbiter frame dispatch internal bus egress data store Network Processors

59 Flexible RISC Plus Coprocessors (Motorola C-Port) Onboard processors can be Dedicated Parallel clusters Pipeline Network Processors

60 C-Port Architecture switching fabric network processor 1 network processor 2... network processor N physical interface 1 physical interface 2 physical interface N Network Processors

61 C-Port Configured As Parallel Clusters SRAM switching fabric SRAM PCI bus serial PROM DRAM queue mgmt. unit fabric proc. table lookup unit pci ser. prom Exec. Processor buffer mgmt. unit multiple onboard buses clusters CP-0 CP-1 CP-2 CP-3... CP-12 CP-13 CP-14 CP-15 connections to physical interfaces Network Processors

62 Internal Structure Of A C-Port Channel Processor To external DRAM memory bus RISC Processor extract space merge space Serial Data Processor (in) Serial Data Processor (out) packets arrive packets leave Actually a processor complex Network Processors

63 General Purpose Processor (Intel) First generation model is IXP1200 One embedded processor (StrongARM) Six programmable packet processors (microengines) Four external bus interconnections Other functional units Network Processors

64 IXP1200 External Connections optional host connection PCI bus SRAM bus SRAM serial line FLASH Memory Mapped I/O IXP1200 chip SDRAM SDRAM bus High-speed I/O bus IX bus Network Processors

65 IXP1200 Internal Architecture optional host connection PCI bus SRAM bus IXP1200 chip SRAM SRAM access PCI access Embedded RISC processor (StrongARM) serial line FLASH Memory Mapped I/O scratch memory multiple, independent internal buses Microengine 1 Microengine 2 Microengine 3 Microengine 4 SDRAM SDRAM access IX access Microengine 5 Microengine 6 SDRAM bus High-speed I/O bus IX bus Network Processors

66 Example Of Complexity: SRAM Access Unit SRAM access unit SRAM clock signals address data SRAM pin interface data service priority arbitration memory & FIFO AMBA bus interface AMBA from StrongARM buffer Flash (Boot ROM) Memory Mapped I/O addr command decoder & addr. generator AMBA addr. queues microengine addr. & command queues Microengine commands microengine data Network Processors

67 A Second Generation Of Network Processors Announced by several vendors Due to emerge in late 2003 Trends Higher data rates (10 Gbps) More functionality Network Processors

68 A Second Generation Of Network Processors (continued) Examples Agere Systems APP 550 and APP 750 IBM enhanced PowerPC Intel IXP 2400 and IXP 2800 Network Processors

69 Open Questions Will network bandwidth or CPU speed increase fastest? Can network processors become as inexpensive as generalpurpose processors? Can network processors become as fast as ASICs? What hardware architecture should be used for network processors? What software architecture should be used for network processors? Network Processors

70 Summary Goal of network processors Flexibility of software-based systems High speed of ASICs Many architectural experiments No consensus on How to provide functionality How to attain highest speed How to architect a switching fabric Which programming language(s) to use Many open problems Network Processors

71 Questions?

72 STOP