Transmission techniques and multiplexing hierarchies

Transcription

1 Transission techniques and ultiplexing hierarchies Switching Technology S L - Transission techniques PDH (Plesiochronous Digital Hierarchy) ATM (Asynchronous Transfer Mode) IP/Ethernet SDH (Synchronous Digital Hierarchy) OTN (Optical Transport network) GFP (Generic Fraing Procedure) L -

2 Plesiochronous Digital Hierarchy (PDH) Transission technology of the digitized teleco network Basic channel capacity 64 kbit/s Voice inforation PCM coded 8 bits per saple A or µ law saple rate 8 khz (5 µs) Channel associated signaling (SS7) Higher order fraes obtained by ultiplexing four lower order fraes bit by bit and adding soe synchr. and anageent info The ost coon switching and transission forat in the telecounication network is PCM 30 (E) E0 E E Mbit/s 90 channels x 4 E Mbit/s 480 channels x 4 E Mbit/s 0 channels x Mbit/s channels x 3 64 kbit/s channel L - 3 PDH E-frae structure (even fraes) Multi- frae F0 F... F4 F5 Voice channels - 5 Voice channels 6-30 T0 T T T0... T5 T6 T7... T8 T9 T30 T3 Frae alignent tie-slot C Signaling tie-slot A Voice channel 8 B B B3 B4 B5 B6 B7 B8 Error indicator bit (CRC-4) Frae alignent signal (FAS) Multi-frae alignent bit sequence in F0 Multi-frae alar Voice saple aplitude Polarity L - 4

3 PDH E-frae structure (odd fraes) Multi- frae F0 F... F4 F5 Voice channels - 5 Voice channels 6-30 T0 T T T0... T5 T6 T7... T8 T9 T30 T3 Frae alignent tie-slot C A D D D D D Error indicator bit (CRC-4) Data bits for anageent Far end alar indication Signaling tie-slot a b c d a b c c Channel signaling bits Channel 6 signaling bits Nowadays, tie slot used for signaling and tie slot 6 for voice L - 5 PDH-ultiplexing Tributaries have the sae noinal bit rate, but with a specified, peritted deviation (00 bit/s for.048 Mbit/s) Plesiochronous = tributaries have alost the sae bit rate Justification and control bits are used in ultiplexed flows First order (E) is octet-interleaved, but higher orders (E, ) are bit-interleaved L - 6

4 PDH network eleents concentrator n channels are ultiplexed to a higher capacity link that carries channels (n > ) ultiplexer n channels are ultiplexed to a higher capacity link that carries n channels cross-connect static ultiplexing/switching of user channels switch switches incoing TDM/SDM channels to outgoing ones L - 7 Exaple PDH network eleents Concentrator Cross-connect n input channels... n > output channels DXC Multiplexer Switch n input channels... n = output channels L - 8

5 Synchronous digital hierarchy STM Gbit/s Major ITU-T SDH standards: - G G.783 STM-64 0 Gbit/s x 4 x 4 STM-6.48 Gbit/s Notice that each frae transitted in 5 µs! STM-4 6 Mbit/s x 4 x 4 STM- 55 Mbit/s L - 9 SDH reference odel MPX DXC MPX Tributaries STM-n R R STM-n STM-n STM-n Tributaries Regeneration section Regeneration section Regeneration section Multiplexing section Multiplexing section Path layer connection - DXC Digital gross-connect - MPX Multiplexer - R Repeater L - 0

6 SDH-ultiplexing Multiplexing hierarchy for plesiochronous and synchronous tributaries (e.g. E and E3) Octet-interleaving, no justification bits - tributaries visible and available in the ultiplexed SDH flow SDH hierarchy divided into two groups: ultiplexing level (virtual containers, VCs) line signal level (synchronous transport level, STM) Tributaries fro E (.048 Mbit/s) to E4 (39.64 Mbit/s) are synchronized (using justification bits if needed) and packed in containers of standardized size Control and supervisory inforation (POH, path overhead) added to containers => virtual container (VC) L - SDH-ultiplexing (cont.) Different sized VCs for different tributaries (e.g. VC-/E, VC- 3/E3, VC-4/E4) Saller VCs can be packed into a larger VC (+ new POH) Section overhead (SOH) added to larger VC => transport odule Transport odule corresponds to line signal (bit flow transferred on the ediu) bit rate is 55.5 Mbit/s or its ultiples transport odules called STM-N (N =, 4, 6, 64,...) bit rate of STM-N is Nx55.5 Mbit/s duration of a odule is 5 µs (= duration of a PDH frae) L -

7 SDH network eleents regenerator (interediate repeater, IR) regenerates line signal and ay send or receive data via counication channels in RSOH header fields ultiplexer terinal ultiplexer ultiplexes/deultiplexes PDH and SDH tributaries to/fro a coon STM-n add-drop ultiplexer adds or drops tributaries to/fro a coon STM-n digital cross-connect used for rearrangeent of connections to eet variations of capacity or for protection switching connections set up and released by operator L - 3 Exaple SDH network eleents Cross-connect STM-n STM-n STM-n DXC STM-n STM-n STM-n Add-drop ultiplexer Terinal ultiplexer STM-n ADM STM-n ADM STM-n - 40 Mbit/s - 40 Mbit/s L - 4

8 Generation of STM- frae Justification PDH/E VC- MUX VC-4 STM- + POH + POH + SOH L - 5 STM-n frae Three ain fields: Regeneration and ultiplexer section overhead (RSOH and MSOH) Payload and path overhead (POH) AU (adinistrative) pointer specifies where payload (VC-4 or VC-3) starts nx9 octets nx6 octets 3 RSOH 5 AU-4 PTR MSOH P O H L - 6

9 Synchronization of payload Position of each octet in a STM frae (or VC frae) has a nuber AU pointer contains position nuber of the octet in which VC starts Lower order VC included as part of a higher order VC (e.g. VC- as part of VC-4) STM- no. k STM- no. k+ RSOH AU-4 PTR MSOH RSOH AU-4 PTR MSOH VC-4 no. 0 VC-4 no. VC-4 no. L - 7 Asynchronous Transfer Mode (ATM) cell 53 octets routing/switching based on VPI and VCI adaptation processing of user data into ATM cells error control cell header checking and discarding flow control no flow control input rate control congestion control cell discarded (two priorities) L - 8

10 ATM reference interfaces NNI UNI ATM network EX TE NNI UNI EX TE - Network-to-Network Interface - User Network Interface - Exchange Equipent - Terinal Equipent L - 9 ATM cell structure 5 octets 48 octets ATM ATM header header Cell Cell payload payload GFC GFC VPI VPI VCI VCI VPI VPI VCI VCI ATM header for UNI VCI VCI HEC HEC PTI PTI ATM header for NNI VPI VPI VCI VCI HEC HEC PTI PTI VPI VPI VCI VCI VCI VCI CPL CPL CPL CPL UNI - User Network Interface NNI - Network-to-Network Interface VPI - Virtual Path Identifier VCI - Virtual Channel Identifier GFC - Generic Flow Control PTI - Payload Type Identifier CPL - Cell Loss Priority HEC - Header Error Control HEC = 8 x (header octets to 4) / (x 8 + x + x + ) L - 0

11 ATM connection types VCI VCI VPI VPI VCI VCI Physical channel VCI VCI VPI VPI VCI VCI VCI k VPI k - Virtual Channel Identifier k - Virtual Path Identifier k L - Physical layers for ATM SDH (Synchronous Digital Hierarchy) STM- 55 Mbit/s STM-4 6 Mbit/s STM-6.4 Gbit/s PDH (Plesiochronous Digital Hierarchy) E Mbit/s E3 34 Mbit/s E4 40 Mbit/s TAXI 00 Mbit/s and IBM 5 Mbit/s Cell based interface uses standard bit rates and physical level interfaces (e.g. E, STM- or STM-4) HEC used for fraing L -

12 Transport of data in ATM cells Network layer ATM adaptation layer (AAL) IP packet AAL 5 payload P UU/ CPI/ LEN Pad 0-47 octets (++ ) octets CRC 4 octets ATM layer 5 48 H Cell payload H Cell payload H Cell payload H Cell payload Physical layer P UU CPI LEN - Padding octets - AAL layer user-to-user indicator - Coon part indicator - Length indicator L - 3 ATM cell encapsulation / SDH 9 octets 6 octets STM- frae 3 SOH VC-4 frae AU-4 PTR J B SOH C G F... H4 Z3 Z4 Z VC-4 POH ATM cell L - 4

13 ATM cell encapsulation / PDH (E) 3 octets TS0 Header TS6 TS0 TS6 Header TS0 TS6 TS0 Header TS6 TS0 TS6 Head.... TS0 frae alignent F3 OAM functions loss of frae alignent perforance onitoring transission of FERF and LOC perforance reporting TS6 reserved for signaling L - 5 Cell based interface Frae structure for cell base interfaces: P L IDLE or PL-OAM H ATM layer H ATM layer... H ATM layer P L IDLE or PL-OAM PL cells processed on physical layer (not on ATM layer) IDLE cell for cell rate adaptation PL-OAM cells carry physical level OAM inforation (regenerator (F) and transission path (F3) level essages) PL cell identified by a pre-defined header (IDLE cell) (phys. layer OAM) xxxx xxxx (reserved for phys. layer) H = ATM cell Header, PL = Physical Layer, OAM = Operation Adinistration and Maintenance L - 6

14 ATM network eleents Gross-connect switching of virtual paths (VPs) VP paths are statically connected Switch switching of virtual channel (VCs) VC paths are dynaically or statically connected DSLAM (Digital Subscriber Line Access Multiplexer) concentrates a larger nuber of sub-scriber lines to a coon higher capacity link aggregated capacity of subscriber lines surpasses that of the coon link L - 7 Ethernet Originally a link layer protocol for LANs (0 and 00 MbE) Upgrade of link speeds => optical versions GbE and 0 GbE => suggested for long haul transission No connections - each data terinal (DTE) sends data when ready - MAC is based on CSMA/CD Synchronization line coding, preable pattern and start-of-frae deliiter Manchester code for 0 MbE, 8B6T for 00 MbE, 8B0B for GbE L - 8

15 Ethernet frae octets Preable S F D DA SA T/L Payload CRC Preable - AA AA AA AA AA AA AA (Hex) SFD - Start of Frae Deliiter AB (Hex) DA - Destination Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC04, IEEE 80.3) indicator CRC - Cyclic Redundance Check Inter-frae gap octets (9,6 µs /0 MbE) L - 9 GbE frae 5-58 octets Preable S F D DA SA L Payload CRC Extension Preable - AA AA AA AA AA AA AA (Hex) SFD - Start of Frae Deliiter AB (Hex) DA - Destination Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC04, IEEE 80.3) indicator CRC - Cyclic Redundancy Check Inter-frae gap octets (96 ns / GbE) Extension - for padding short fraes to be 5 octets long L - 30

16 Ethernet network eleents Repeater interconnects LAN segents on physical layer regenerates all signals received fro one segent and forwards the onto the next Bridge interconnects LAN segents on link layer (MAC) all received fraes are buffered and error free ones are forwarded to another segent (if they are addressed to it) Hub and switch hub connects DTEs with two twisted pair links in a star topology and repeats received signal fro any input to all output links switch is an intelligent hub, which learns MAC addresses of DTEs and is capable of directing received fraes only to addressed ports L - 3 Optical transport network Optical Transport Network (OTN), being developed by ITU-T (G.709), specifies interfaces for optical networks Goal to gather for the transission needs of today s wide range of digital services and to assist network evolution to higher bandwidths and iproved network perforance OTN builds on SDH and introduces soe refineents: anageent of optical channels in optical doain FEC to iprove error perforance and allow longer link spans provides eans to anage optical channels end-to-end in optical doain (i.e. no O/E/O conversions) interconnections scale fro a single wavelength to ultiple ones L - 3

17 OTN reference odel OMPX OMPX Optical channels OA OA Optical channels OTS OTS OTS OMS OCh - OCh Optical Channel - OA Optical Aplifier - OMS Optical Multiplexing Section - OMPX Optical Multiplexer - OTS Optical Transport Section L - 33 OTN layers and OCh sub-layers SONET/ SDH ATM Ethernet IP Optical channel Optical ultiplexing section (OMSn) OPU Optical channel payload unit ODU Optical channel data unit OTU Optical channel transport unit Optical transport section (OTSn) L - 34

18 OTN frae structure Three ain fields Optical channel overhead Payload Forward error indication field GbE ATM/FR IP FR SONET/SDH ATM GbE IP SONET/SDH DWDM Och Payload FEC Client Digital wrapper L - 35 OTN frae structure (cont.) 4080 bytes rows Och overhead Payload FEC Frae alignt. ODU overhead OTU overhead OTU - Optical transport unit ODU - Optical data unit OPU - Optical payload unit FEC - Forward error correction OPU overh. Frae size reains the sae (4x4080) regardless of line rate => frae rate increases as line rate increases Three line rates defined: OTU.666 Gbit/s OTU Gbit/s OTU Gbit/s L - 36

19 Generation of OTN frae and signal OTN frae generation Client signal OPU ODU OTU + OPU-OH + OTU-OH + FEC OTN signal generation Client signal Client signal OCh OCh OMUX OMS OTS L - 37 OTN network eleents optical aplifier aplifies optical line signal optical ultiplexer ultiplexes optical wavelengths to OMS signal add-drop ultiplexer adds or drops wavelengths to/fro a coon OMS optical cross- connect used to direct optical wavelengths (channels) fro an OMS to another connections set up and released by operator optical switches? when technology becoes available optical switches will be used for switching of data packets in the optical doain L - 38

20 Generic Fraing Procedure (GFP) Recently standardized traffic adaptation echanis especially for transporting block-coded and packet-oriented data Standardized by ITU-T (G.704) and ANSI (T.05.0) (the only standard supported by both organizations) Developed to overcoe data transport inefficiencies of existing ATM, POS, etc. technologies Operates over byte-synchronous counications channels (e.g. SDH/SONET and OTN) Supports both fixed and variable length data fraes Generalizes error-control-based frae delineation schee (successfully eployed in ATM) relies on payload length and error control check for frae boundary delineation L - 39 GFP (cont.) Two frae types: client and control fraes client fraes include client data fraes and client anageent fraes control fraes used for OAM purposes Multiple transport odes (coexistent in the sae channel) possible Frae-apped GFP for packet data, e.g. PPP, IP, MPLS and Ethernet) Transparent-apped GFP for delay sensitive traffic (storage area networks), e.g. Fiber Channel, FICON and ESCON L - 40

21 GFP client data frae Coposed of a frae header and payload Core header intended for data link anageent payload length indicator (PLI, octets), HEC (CRC-6, octets) Payload field divided into payload header, payload and optional FCS (CRC-3) sub-fields Payload header includes: payload type ( octets) and type HEC ( octets) sub-fields optional 0-60 octets of extension header Payload: variable length ( octets, including payload header and FCS) for frae apping ode (GFP-F) - frae ultiplexing fixed size Nx[536, 50] for transparent apping ode (GFP-T) - no frae ultiplexing L - 4 GFP frae structure Core header Payload length indicator Core HEC Payload header Payload type Type HEC 0 60 bytes extension header (optional) PTI PFI EXI UPI CID Spare Extension HEC MSB Extension HEC LSB Payload area Payload [N x 536, 50 bytes or variable length packet] Payload FCS CID - Channel identifier FCS - Frae Check Sequence EXI - Extension Header Identifier HEC - Header Error Check PFI - Payload FCS Indicator PTI - Payload Type Indicator UPI - User payload Identifier Source: IEEE Counications Magazine, May 00 L - 4

22 GFP relationship to client signals and transport paths Ethernet IP/PPP Frae apped MAPOS RPR Fiber Channel FICON GFP client-dependent GFP client-independent ESCON Other client signals Transparent apped SDH/SONET path OTN ODUk path ESCON - Enterprise Syste CONnection FICON - Fiber CONnection IP/PPP - IP over Point-to-Point Protocol MAPOS - Multiple Access Protocol over SONET/SDH RPR - Resilient Packet Ring Source: IEEE Counications Magazine, May 00 L - 43 Adapting traffic via GFP-F and GFP-T GFP-F frae PLI chec bytes bytes Payload header 4 bytes Client PDU (PPP, IP, Ethernet, RPR, etc.) FCS (optional) 4 bytes GFP-T frae PLI chec bytes bytes Payload header 4 bytes 8x64B/65B superblock # #... #N- #N FCS (optional) 4 bytes FCS chec PDU PLI - Frae Check Sequence - Core Header Error Control - Packet Data Unit - Payload Length Indicator L - 44

23 GFP-T frae apping 64B/65B code block 8B 8B 8B 8B 8B 8B 8B 8B 8 x 64B/65B code blocks Superblock (8 x 64B/65B code blocks + CRC-6) CRC-6 GFP-T frae with five superblocks Core header and payload header FCS (optional) L - 45 Switch Fabrics Switching Technology S L - 46

24 Switch fabrics Basic concepts Tie and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search L - 47 Switch fabrics (cont.) Multi-point switching Self-routing networks Sorting networks Fabric ipleentation technologies Fault tolerance and reliability L - 48

25 Basic concepts Accessibility Blocking Coplexity Scalability Reliability Throughput L - 49 Accessibility A network has full accessibility (= connectivity) when each inlet can be connected to each outlet (in case there are no other I/O connections in the network) A network has a liited accessibility when the above given property does not exist Interconnection networks applied in today s switch fabrics usually have full accessibility L - 50

26 Accessibility (cont.) Exaple of full accessibility Exaple of liited accessibility L - 5 Blocking Blocking is defined as failure to satisfy a connection request and it depends strongly on the cobinatorial properties of the switching networks Network class Network type Network state Non-blocking Blocking Strict-sense non-blocking Wide-sense non-blocking Rearrangeably non-blocking Others Without blocking states With blocking state L - 5

27 Blocking (cont.) Non-blocking - a path between an arbitrary idle inlet and arbitrary idle outlet can always be established independent of network state at set-up tie Blocking - a path between an arbitrary idle inlet and arbitrary idle outlet cannot be established owing to internal congestion due to the already established connections Strict-sense non-blocking - a path can always be set up between any idle inlet and any idle outlet without disturbing paths already set up Wide-sense non-blocking - a path can be set up between any idle inlet and any idle outlet without disturbing existing connections, provided that certain rules are followed. These rules prevent network fro entering a state for which new connections cannot be ade Rearrangeably non-blocking - when establishing a path between an idle inlet and an idle outlet, paths of existing connections ay have to be changed (rearranged) to set up that connection L - 53 Exaples of different sorts of blocking networks Blocking Rearrangeably non-blocking Strict-sense non-blocking Strict-sense non-blocking L - 54

28 Coplexity Coplexity of an interconnection network is expressed by cost index Traditional definition of cost index gives the nuber of crosspoints in a network used to be a reasonable easure of space division switching systes Nowadays cost index alone does not characterize cost of an interconnection network for broadband applications VLSIs and their integration degree has changed the way how cost of a switch fabric is fored (nuber of ICs, power consuption) anageent and control of a switching syste has a significant contribution to cost L - 55 Coplexity (cont.) Cost index of an 8x8 crossbar is 64 (cross-points) Cost index of an 8x8 banyan is x4= 48 (cross-points) L - 56

29 Scalability Due to constant increase of transport links and data rates on links, scalability of a switching syste has becoe a key paraeter in choosing a switch fabric architecture Scalability describes ability of a syste to evolve with increasing requireents Issues that are usually atter of scalability nuber of switching nodes nuber of interconnection links between nodes bandwidth of interconnection links and inlets/outlets throughput of switch fabric buffering requireents nuber of inlets/outlets supported by switch fabric L - 57 Scalability (cont.) Exaple of scalability a switching equipent has roo for 0 line-cards and the original design supports 0 Mbit/s interfaces (one per line card) throughput of switch fabrics is scalable fro 500 Mbit/s to Gbit/s when new line cards that each ipleent two 0 Mbit/s interfaces are introduced, the interface logic ay have to be upgraded when new line cards that ipleent a 00 Mbit/s interface (one per linecard) are introduced, the switch fabric has to be upgraded (scaled up) to Gbit/s speed and the interface logic has to be upgraded to 00 Mbit/s speed buffering eories need to be replaced by faster (and possible larger) ones larger nuber (>0) of line cards iplies at least new physical design increase of line rates beyond 00 Mbit/s eans redesign of switch fabric L - 58

30 Reliability Reliability and fault tolerance are syste easures that have an ipact on all functions of a switching syste Reliability defines probability that a syste does not fail within a given tie interval provided that it functions correctly at the start of the interval Availability defines probability that a syste will function at a given tie instant Fault tolerance is the capability of a syste to continue its intended function in spite of having a fault(s) Reliability easures: MTTF (Mean Tie To Failure) MTTR (Mean Tie To Repair) MTBF (Mean Tie Between Failures) L - 59 Throughput Throughput gives forwarding/switching speed/efficiency of a switch fabric It is easured in bits/s, octets/s, cells/s, packet/s, etc. Quite often throughput is given in the range (0....0], i.e. the obtained forwarding speed is noralized to the theoretical axiu throughput L - 60

31 Switch fabrics Basic concepts Tie and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search L - 6 Switching echaniss A switched connection requires a echanis that attaches the right inforation streas to each other Switching takes place in the switch fabric, the structure of which depends on network s ode of operation, available technology and required capacity Counicating terinals ay use different physical links and different tie-slots, so there is an obvious need to switch both in tie and in space doain Tie and space switching are basic functions of a switch fabric L - 6

32 Space division switching A space switch directs traffic fro input links to output links An input ay set up one connection (, 3, 6 and 7), ultiple connections (4) or no connection (, 5 and 8) INPUTS OUTPUTS INPUT LINKS INTERCONNECTION NETWORK n OUTPUT LINKS L - 63 Crossbar switch atrix Crossbar atrix introduces the basic structure of a space switch Inforation flows are controlled (switched) by opening and closing cross-points inputs and n outputs => n cross-points (connection points) Only one input can be connected to an output at a tie, but an input can be connected to ultiple outputs (ulti-cast) at a tie INPUT LINKS MULTI-CAST A CLOSED CROSS-POINT n OUTPUT LINKS L - 64

33 An exaple space switch x -ultiplexer used to ipleent a space switch Every input is fed to every output ux and ux control signals are used to select which input signal is connected through each ux ux/connection control x x x L - 65 Tie division ultiplexing Tie-slot interchanger is a device, which buffers incoing tieslots, e.g. 30 tie-slots of an E frae, arranges new transit order and transits n tie-slots Tie-slots are stored in buffer eory usually in the order they arrive or in the order they leave the switch - additional control logic is needed to decide respective output order or the eory slot where an input slot is stored TIME-SLOT INTERCHANGER INPUT CHANNELS Tie-slot Tie-slot Tie-slot 3 OUTPUT CHANNELS Tie-slot 4 Tie-slot 5 Tie-slot 6 BUFFER SPACE FOR TIME-SLOTS L - 66

34 Tie-slot interchange DESTINATION OUTPUT # BUFFER FOR INPUT/OUTPUT SLOTS INPUT LINKS (3) () 5 4 (4) 3 (,6) (5) n OUTPUT LINKS L - 67 Tie switch ipleentation exaple Incoing tie-slots are written cyclically into switch eory Output logic reads cyclically control eory, which contains a pointer for each output tie-slot Pointer indicates which input tie-slot to insert into each output tie-slot Incoing frae buffer Cyclic read 3 write address (3) Switch eory 3. k. read address (k) Control eory 3. j (k). n Outgoing frae buffer n j read/write address (j) Cyclic write Tie-slot counter & R/W control L - 68

35 Tie switch ipleentation exaple Incoing tie-slots are written into switch eory by using write-addresses read fro control eory A write address points to an output slot to which the input slot is addressed Output tie-slots are read cyclically fro switch eory Incoing frae buffer Cyclic read 3 read address (3) Control eory 3 (k). write address (k) Switch eory 3. k. n Outgoing frae buffer n j Cyclic write read/write address () Tie-slot counter & R/W control L - 69 Properties of tie switches Input and output frae buffers are read and written at wire-speed, i.e. R/Ws for input and n R/Ws for output Interchange buffer (switch eory) serves all inputs and outputs and thus it is read and written at the aggregate speed of all inputs and outputs => speed of an interchange buffer is a critical paraeter in tie switches and liits perforance of a switch Meory speed requireent can be cut by utilizing parallel to serial conversion Speed requireent of control eory is half of that of switch eory (in fact a little oor than that to allow new control data to be updated) L - 70

36 Tie-Space analogy A tie switch can be logically converted into a space switch by setting tie-slot buffers into vertical position => tie-slots can be considered to correspond to input/output links of a space switch But is this logical conversion fair? Space switch Tie switch 3 n L - 7 Space-Space analogy A space switch carrying tie ultiplexed input and output signals can be logically converted into a pure space switch (without cyclic control) by distributing each tie-slot into its own space switch Inputs and outputs are tie ultiplexed signals (K tie-slots) n n n To switch a tie-slot, it suffices to control one of the K boxes K n L - 7

37 An exaple conversion K ultiplexed input signals on each link n xn KxK nx K n K L - 73 Properties of space and tie switches Space switches nuber of cross-points (e.g. ANDgates) - input x n output = n - when =n => n output bit rate deterines the speed requireent for the switch coponents both input and output lines deploy bus structure => fault location difficult Tie switches size of switch eory (SM) and control eory (CM) grows linearly as long as eory speed is sufficient, i.e. SM + CM + input buffering + output buffering = x x nuber of tie-slots a siple and cost effective structure when eory speed is sufficient speed of available eory deterines the axiu switching capacity L - 74