256MEGX72 (DDR2-SOCDIMM W/PLL)

Transcription

1 MEMORY SPECIFICATIONS 256MEGX72 (DDR2-SOCDIMM W/PLL) 128MX8 BASED Lead-Free 268,435,456 words x 72Bit Double Data Rate Memory Module Centon's 2GB DDR2 ECC PLL SODIMM Memory Module is 268,435,456 words by 72Bit Double Data Rate Memory Module which is assembled with 18 pieces of a 128MX8Bit, FBGA Double Data Rate, and 1 piece zero delay PLL clock in VF-BGA on the printed circuit board. The module is optimized for high density and large capacity in a compact size. 256MEGX72 (DDR2 SOCDIMM) - 2GB

2 CPCB Pinout Information 1 VREF CB CB Pin Name Function A0 ~ A13 Address input CB CB Row=A0-A13,Col=A0-A CB BA0 ~BA2 Bank Select Address CB ~3 Data input/output ~ 8 Data Strobe CB ~8 Data Strobes Complement 21 DQ CKE0 88 CB DQ CKE CK0,CK0 Clock Inputs NC/CS2* 92 BA CKE0,CKE1 Clock Enable input VDD 94 A14* CS0,CS1 Chip Select input A12 96 A RAS Row Address Strobe A9 98 VDD CAS Column Address Strobe A7 100 A WE Write Enable VDD 102 A A5 104 A ~ 8 Data-in mask A3 106 VDD VDD Power Supply KEY 107 A2 108 A Ground RESET 109 VDD 110 A VREF Power supply for reference A10/AP 112 BA VDDSPD Serial EEPROM Power Supply( V) BA0 114 VDD Serial Data I/O RAS 116 WE VDD 118 CS Serial Clock CAS 120 ODT SA0 ~ SA1 Address in EEPROM CS1 122 A ODT0,ODT1 On-die termination control VDD ODT1 124 VDD 126 CK RESET Reset Input NC/CS3* CK SA1 CB0~CB7 Check Bits VDDSPD 200 SA Note: * : these pins are not used in this module. NC : these pins are not connect. 256MEGX72 DDR2-2GB FEATURES * 268,435,456 words by 72 bits organization * Utilizes 333MHz Double Data Rate components * CAS Latency specified in the performance table * Support ECC error detection and correction * Single power supply of 1.8V +/-.1V * VDDSPD= 1.7V-3.6V * ODT(On Die Termination) * On memory PLL Clock * Fully Synchronous with all signals registered to positive and negative edge of clock * Serial Presence Detect with EEPROM (VDDSPD=1.7V to 3.6V) * Burst length; 4, 8 * 7.8us maximum average periodic refresh interval * Auto and Self refresh capability * SSTL_18 Interface * 200 pin SODIMM JEDEC Proposed compatible * RoHS Compliant PERFORMANCE RANGE TYPE MAX FREQ. DDR Mhz CL5) COMPATIBILITY Centon s 2GB DDR2 SOCDIMM Memory Module is fully compatible with industry standard 200 pin SODIMM, ECC PLL DDR2 Memory Modules. APPLICATION High Density Memory Unit for Personal Computers, Workstations and Servers. ENVIRONMENT OPERATING STORAGE TEMPERATURE 0 o C to 85 o C -55 o C to 125 o C HUMIDITY 20% to 80% 5% to 80% WARRANTY Centon will repair or replace any Centon memory product that fails due to defective material or workmanship under normal use for the life of the product. DDR Mhz CL4)

3 Block Diagram CS1 CS DQ8 DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 A0-An BA0-BA2 WE RAS CAS ODT0 ODT1 CKE0 CKE1 CS U1 U2 U3 CS U4 U9 U10 U11 U12 CS U13 U18 CK0,CK * See Differential Clock Net Wiring. VDDSPD VDD/VDDQ VREF A0-An, DDR2 s U1-U18 BA0-BA1, DDR2 s U1-U18 /WE, DDR2 s U1-U18 /RAS, DDR2 s U1-U18 /CAS, DDR2 s U1-U18 ODT0, DDR2 s U1-U9 ODT0, DDR2 s U10-U18 CKE0, DDR2 s U1-U9 CKE1, DDR2 s U10-U18 *PLL U5 U6 U7 U8 SPD WP A0 U14 U15 U16 U17 SPD A1 SA0 SA1 A2 DDR2 s U1-U18 DDR2 s U1-U18 DDR2 s U1-U18

4 Differential Clock Wiring Diagram PLL OUT1 CK0 CK0 C IN OUT 'N' C Feedback 1. The clock delay from the input of the PLL clock to the input of any or register will be set to 0ns (nominal). 2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.

5 Mechanical/Assembly Drawing CENTON NORTHEAST TEL: (631) (800) FAX: (631) CENTON SOUTHWEST TEL: (949) (800) FAX: (949)