Xilinx Solutions for PCI Express

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1 Xilinx Solutions for PCI Express

2 Agenda PCI Express Overview Why PCI Express? Key Requirements PCI Express Layered Architecture Physical Data Link Transaction Software Mechanical PCI Express Application Examples Xilinx Solutions for PCI Express Slide 2

3 PCI Express Overview Third-generation PCI based I/O specification Formerly known as 3GIO and Arapahoe I/O interconnect for wide variety of future computing and communications platforms Fully-serial interface instead of parallel bus Maintains usage models and software interfaces of PCI Slide 3

4 Today s Platform CPU (Client configuration) Processor System Bus Graphics AGP Memory Bridge Memory HubLink or others HDD ATA I/O Bridge USB1.1 Local I/O PCI Diverging Requirements for Each of the Interconnects Next Generation I/O bus should replace most of the inside-the-box interconnects Slide 4

5 PCI Bus Slide 5

6 PCI Express Performance PCI Express Courtesy: Microprocessor Report, September 2001 Best Bandwidth/Pin => Best Value Slide 6

7 Why PCI Express? Traditional I/O interconnects at practical limits Lack of scaling with frequency and voltage Strict skew requirements between parallel signals Stringent routing rules When measured as % of total system cost Look beyond today s specific solutions Must comprehend the requirements of multiple market segments and is ISA good for for the next decade EISA MCA VESA PCI 1980 s 1990 s AGP PCI-X HL Others Need a new Industry Standard Interconnect Slide 7

8 Key Requirements Low cost, high volume Cost at or below PCI cost structure at system level Supports multiple market segments Unifying I/O interconnect technology for Desktop, Mobile, Server, Communication platforms, Workstations and Embedded PCI compatible software model Boot Operating Systems, Configuration/Device Driver Interfaces Performance Scalable performance High Bandwidth/pin, Low overhead and Low latency Slide 8

9 PCI Express Requirements Cost effective Cost at or below PCI Cost structure at system level Utilize high volume system ingredients: Silicon, boards, connectors Support multiple market segments and applications Mobile, Desktops, Servers and Communication Devices Balance performance and feature set by segment Stable, Scalable and Extensible Suitable for future applications and technologies over ~10years Support advanced features and performance Power management, QoS, Hot Attach/Detach, RAS Compatible with PCI Architecture and Infrastructure Boot existing OSs without any changes Utilize existing system infrastructure without any changes Slide 9

10 PCI Express Layered Architecture Config/OS S/W PCI PnP Model (init, enum, config) PCI Software/Driver Model No OS impact Transaction Packet-based Protocol Data Link Physical (electrical Mechanical) Data Integrity Point to point, serial, 2.5+ Gb/s differential, hot-plug, inter-op form factors > 2.5Gb/s/port/direction Future speeds & encoding techniques only impact the Physical layer PCI Express Layering Enables Scalability, Modularity and Reuse Slide 10

11 Functional Elements Slide 11

12 PHY Layer Basics Logical Functions Encoding/decoding Reset, initialization, de-skew Built in test modes Configuration Speed, Link width, lane mapping, polarity Electrical Functions Transmitter/Receiver Packet Exchange Link Power management Slide 12

13 Physical Layer Clock Device A Selectable Width Device B Clock Point to point differential interconnect Low Voltage Signaling Two unidirectional links, No Sideband Signals Bit rate: > 2.5Gb/s/pin/dir and beyond Clocking: Embedded clock signaling using 8b/10b encoding Interface Width: Per direction: x1, x2, x4, x8, x12, x16, x32 Hot add/remove electrical support Slide 13

14 Signaling Basics Differential Superior voltage margins to single-ended Voltage independence; VCC can vary Reduced EMI issues Serial Lanes Higher frequency removes skew requirements between parallel lanes Relaxed routing rules; 4 layer FR4 boards; 20-30, 2 connectors Slide 14

15 8b/10b Encoding Embedded clocking through bit transitions Clock recovery at receiver Supplemental coverage through 8b/10b Higher Performance Routing Flexibility Slide 15

16 Transaction Layer Based on Load Store Architecture Common flat PCI 32/64 bit addressing model Split-transaction, packet based protocol Credit based flow control PCI-X like producer-consumer ordering rules Transaction level End to End CRC Slide 16

17 Data Link Layer Reliable data transport services 32-bit CRC generation and detection Error causes link-level retry Loss of packets detected using sequence numbers Slide 17

18 Packet Formation Slide 18

19 ... Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 PCI Express Transfers Byte Stream {conceptual}... Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Byte 3 Byte 2 Byte 1 Byte 0 Byte 4 Byte 0 Byte 5 Byte 1 Byte 6 Byte 2 Byte 7 Byte 3 8b/10b P > S 8b/10b P > S 8b/10b P > S 8b/10b P > S 8b/10b P > S Lane 0 Lane 0 Lane 1 Lane 2 Lane 3 Bandwidth is selectable using multiple lanes Slide 19

20 PCI Express Advanced Features Quality of Service Enhancements Virtual channels and traffic classifications Predictable latencies and Isochronous data transfers Relaxed ordering and no-snoop transactions Peer-to-Peer transfers Multi hierarchy and advanced switching support Slide 20

21 PCI Express Advanced Features Rich set of error logging & reporting Aggressive power management Power Budgeting Hot attach / surprise removal capability Miscellaneous side-band signals replaced with in-band messages Error signaling, power management, legacy interrupts Built in ease of testing Slide 21

22 Enhanced Configuration Space Layout PCI Express improves and extends existing PCI concepts Slide 22

23 Software Layers PCI software Model compatible 100% OS and driver level compatible PCI enumeration, configuration, and power management mechanisms Existing Operating Systems boot with no changes (inc. BIOS) PCI Express hierarchy mapped using PCI elements: Host-bridges P2P bridges Simple functions All enumerated using PCI device configuration space PCI capability pointer for PCI Express specific extensions Enhanced features enabled by future applications Slide 23

24 Protocol/Software Summary PCI Express advances overall platform while preserving PCI investments PCI Express Layering provides architecture longevity Defined to boot PCI 2.2 compliant OSs unmodified Preserves PCI architecture while addressing basic limitations by defining new features Traffic classes, Isochrony & QoS Native Hot-plug/Surprise removal Advanced RAS/Error Reporting In Band messages Hooks to enable advanced switching Slide 24

25 Evolutionary Form Factor PCI Express Connector Existing PCI Connector High bandwidth concept Slide 25

26 Evolutionary Form Factor PCI Express Connector Existing PCI Connector High bandwidth concept Slide 26

27 Revolutionary Form Factor Short cable concept for desktop/mobile Slide 27

28 Revolutionary Form Factor Today s Add-in Card with large connector Example: Mini-PCI Express BTO/CTO Addin Card with wired functionality Small form factor concept Slide 28

29 Mechanical Summary PCI Express is optimized for cost Cost effective for migration into commodity infrastructure Replaces PCI over time with 10+ years of life PCI Express is easy to implement Does not require chassis changes in desktops and servers Transition to existing PCI form factors PCI Express provides opportunities for innovative design Benefits for Industry and end users Slide 29

30 PCI Express Application Examples

31 Desktop Example Low Cost Maximize reuse: design, validation 4 Layer Motherboard Software PCI compatible software model Performance Width: x1 and x16 interface Isochrony done right Physical Card and module form factors Hot attach/detach Power Budgeting Slide 31

Server Example RAS Capabilities: 32 bit end to end CRC protection & link level retry Error logging and reporting PCI SW compatible Power Budgeting Performance and scalability Lower

32 Server Example RAS Capabilities: 32 bit end to end CRC protection & link level retry Error logging and reporting PCI SW compatible Power Budgeting Performance and scalability Lower system latency and high bandwidth Better Connectivity and fan out True QoS and Virtual Channels Physical Max. Trace length -> 2X PCI-X Lane Reversal New signaling medium possibilities Slide 32

33 Communications Example Advanced Switching Features Multi-hierarchy support, peer-to-peer switching, QoS features Advanced switching and message passing primitives Enables development of sophisticated upper layer protocols Slide 33

34 PCI Express Roadmap Slide 34

35 Xilinx Solutions for PCI Express

36 Xilinx has a Rich PCI Heritage PCI Express will be part of it Q3 2002! Aggregate Bandwidth Mb/sec bit 33MHz Xilinx PCI Performance 64-bit 66MHz 64-bit 66MHz 1 Gbps Fibre Channel Ethernet 64-bit 133MHz Roadmap 2.5 Gbps Ultra 320 SCSI 2Gbps Fibre Channel Internet Backbone 40 Gbps Ethernet 10 Gbps Fibre Channel Ethernet Slide 36

37 Xilinx REAL PCI Express IP Solution Industries first PCI Express IP core fully implemented and tested in Virtex-II Pro FPGAs Utilizing embedded Rocket I/O multi-gigabit transceiver Clock data recovery, 8B/10B encoding, Gbps SerDes, transmit/receive FIFOs and CRC to achieve a 2.5 Gbps line speed Xilinx solution allows designers to track emerging PCI specifications A Winning Solution: Xilinx PCI Express IP Core + V-II Pro Slide 37

38 Xilinx REAL PCI Express Solution Roadmap Available Q to allow early adopters of next generation systems to get their product to market faster Compatible with the PCI Express base specification v1.0 PCI-Express Communication HW Demo target for September Xilinx PCI-Express Hardware Development Platform Opens new markets for using FPGAs networking and server applications Slide 38

Introducing Virtex-II Pro Virtex-II Logic, Routing, Features Upward compatible, same design tools Embedded Multipliers, SelectIO-Ultra (with 840Mbps LVDS), DCI/XCITE, DCM Up to 16, 3.

39 Introducing Virtex-II Pro Virtex-II Logic, Routing, Features Upward compatible, same design tools Embedded Multipliers, SelectIO-Ultra (with 840Mbps LVDS), DCI/XCITE, DCM Up to 16, Gbps serial transceivers Channel bonding, 8b/10b encoding Supports high-speed interfaces PCI Express, GbE, 10GbE (XAUI), PCI/PCI-X, Infiniband, RapidIO, HyperTransport, FlexBus 3/4, POS-PHY 3/4 Up to four IBM 405 PowerPC 32-bit RISC CPU: MHz The leading embedded CPU architecture in telecom & networking infrastructure IBM CoreConnect on-chip bus Virtex-II Pro and IP Solutions will Further Enable Next Generation Networking and Telecom Products Slide 39

V-II Pro manages transition to Serial I/Fs - PCI to PCI Express Reg OCK1 Reg OCK2 Reg OCK1 Reg OCK2 DDR mux 3-State DDR mux Output IOB Input Reg ICK1 Reg ICK2 PAD SelectI/O-Ultra technology for

40 V-II Pro manages transition to Serial I/Fs - PCI to PCI Express Reg OCK1 Reg OCK2 Reg OCK1 Reg OCK2 DDR mux 3-State DDR mux Output IOB Input Reg ICK1 Reg ICK2 PAD SelectI/O-Ultra technology for parallel interfaces 25 I/O Standards XCITE Technology 840 Mbps LVDS Dedicated DDR Registers 78 MHz Gb Serial Transceiver Gb Serial Transceiver 78 MHz DDR FF P N IOB Rocket I/O Multi-Gigabit Serial Transceivers Up to Sixteen Gbps transceivers Helps preserve investment in legacy designs Eases transition from parallel to serial technology Parallel interface designs will not go away Slide 40

41 Supporting Legacy & Evolving System Interfaces QDR SRAM NoBL/ZBT SRAM SDR/DDR SDRAM FCRAM Sigma RAM RLDRAM CAMs PCI 32/64 10/100 Ethernet (MII) Proprietary Xilinx Virtex-II family of FPGAs Serial RapidIO Infiniband PCI Express Fibre Channel 10 Gbit Ethernet (XAUI) RapidIO POS-PHY L3/L4 FlexBus 3/4 CSIX HyperTransport SPI4 Phase1, Phase2 Gigabit Ethernet - GMII 10 Gbit Ethernet (XGMII) 840Mbps LVDS Proprietary Slide 41

Virtex-II Pro Architectural Features 18 Bit 36 Bit BRAM 50 50 18 Bit Impedance Controller Embedded DSP functionality - up to 500 Billion MAC/s Embedded Dual-Port RAM - for Data Buffering XCITE

42 Virtex-II Pro Architectural Features 18 Bit 36 Bit BRAM Bit Impedance Controller Embedded DSP functionality - up to 500 Billion MAC/s Embedded Dual-Port RAM - for Data Buffering XCITE Digitally-Controlled Impedance (DCI) for simpler PCB layout CLKIN CLK0 CLK90 CLKFB CLK180 CLK2X RST CLK270 DSSEN CLK2X180 PSINCDEC CLKDV CLKFX180 PSEN CLKFX PSCLK STATUS[7:0] LOCKED PSDONE clock signal control signal Digital Clock Management (DCM) - Precise Clock Generation Delay (ps) XL LUTs Reached Virtex Virtex-II Φαστεστ ΦΠΓΑ ον τηε Πλανετ Active Interconnect Technology with a 300 MHz System Clock SelectIO 25 IO types including 840 Mbps LVDS Slide 42

43 Summary PCI Express - A 3rd generation follow-on to PCI Unifying I/O interconnect technology for Desktop, Mobile, Server, Communication platforms, Workstations and Embedded Chip-to-chip, board-to-board (plug-in adapters), docking PCI compatible software model Configuration and device driver interface, Boots existing OS s Advanced Features Power management, QoS, Hot Attach/Detach, RAS Performance Industry leading performance and price/performance High Bandwidth/pin, Low overhead and Low latency V-II Pro PCI Express Core coming Q3 2002! Slide 43

44 References White Paper Creating a Third Generation I/O Architecture Why Paper Why build products based on 3GIO Slide 44

45 PCI Express Performance BW/Pin = Peak Bandwidth/Total # the component Total # Pins = Data pins + Address/Control Pins + Power and Ground Pins Assumptions: 32bit, 33MHz & 84pins -> ~133MB/Sec 64bit, 133MHz & 150pins -> ~1GB/Sec bit, 4x 66 MHz & 108pins -> ~1GB/Sec PCI 8 bits/dir, 2.5Gb/s/dir & 40 pins -> ~2.5GB/Sec/Dir Slide 45

46 Questions?

PCI EXPRESS TECHNOLOGY. Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology

PCI EXPRESS TECHNOLOGY. Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology WHITE PAPER February 2004 PCI EXPRESS TECHNOLOGY Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology Formerly known as 3GIO, PCI Express is the open