DVI I/O FMC Module Hardware Guide

Transcription

1 DVI I/O FMC Module Hardware Guide

2 Table of Contents 1.0 Introduction Description Features Ordering Information References Functional Description FMC Voltage Sources I2C Chain 1 IPMI Identification EEPROM I2C Chain 2 Peripheral Configuration Video Clock Synthesizer DVI Input DVI Output DisplayPort Output GPIO Known Issues & Limitations PG_C2M GA[0:1] Revisions Figures Figure 1 DVI I/O FMC Module, Top... 3 Figure 2 DVI I/O FMC Module, Block Diagram... 5 Figure 3 IPMI Identification, Block Diagram... 9 Figure 4 I2C Peripheral Configuration, Block Diagram Figure 5 Video Clock Synthesizer, Block Diagram Figure 6 DVI Input, Block Diagram Figure 7 DVI Output, Block Diagram Figure 8 DisplayPort Output, Block Diagram Figure 9 GPIO, Block Diagram Figure 10 GPIO, PCIe to DisplayPort adapter board (Use Case) Figure 11 FMC-DVI, PG_C2M related components (R39 unpopulated) Tables Table 1 - Ordering Information... 4 Table 2 FMC LPC Pinout... 6 Table 3 DVI I/O FMC Module, FMC Pinout... 7 Table 4 DVI I/O FMC Module, Voltage Sources... 8 Table 5 IPMI Identification, I2C EEPROM Address Table 6 IPMI Identification, GA[0:1] mapping for FMC carriers Table 7 IPMI Identification, EEPROM Content Table 8 I2C Peripheral Configuration, Device Summary Table 9 Video Clock Generator, Clock Output Usage Table 10 DisplayPort Output, CDCM61002 Configuration Options Avnet Electronics Marketing 2 of 19 Rev 1.0

3 1.0 Introduction The purpose of this manual is to describe the functionality and contents of the DVI I/O FMC Module from Avnet Electronics Marketing. This document includes descriptions of the hardware features. 1.1 Description The DVI I/O FMC Module is not a stand-alone module, but rather a plug-in module designed to interface with FMC compatible baseboards. In that role, the DVI I/O FMC Module provides a number of video interfaces to its host via a LPC FMC connector. The DVI I/O FMC Module is shown in Figure 1 and Error! Reference source not found Features The DVI I/O FMC Module provides the following features. Video Input DVI input interface (HDMI connector) Video Output DVI output interface (HDMI connector) DisplayPort output interface Clock Source Video clock synthesizer I2C Configuration IPMI Identification EEPROM Peripheral configuration Other I/O General-purpose I/O pins Figure 1 DVI I/O FMC Module, Top Avnet Electronics Marketing 3 of 19 Rev 1.0

4 1.3 Ordering Information The following table lists the evaluation kit part numbers and available software options. Internet link at Part Number AES-FMC-DVI-G Table 1 - Ordering Information Hardware DVI I/O FMC Module 1.4 References Texas Instruments TFP410 datasheet: PanelBus DVI Transmitter 165 MHz Texas Instruments TFP403 datasheet: PanelBus DVI Receiver 165 MHz Texas Instruments CDCE913 datasheet: Programmable 2-PLL VCXO Clock Synthesizer Texas Instruments CDCM61002 datasheet: Ultra Low Jitter Clock Generator Texas Instruments PCA9546A datasheet: 4-Channel I2C Multiplexer with Reset Texas Instruments SN74AVCH16T245 datasheet: 16-Bit Dual Supply Bus Transceiver Texas Instruments SN74AVCH20T245 datasheet: 20-Bit Dual Supply Bus Transceiver Texas Instruments TPS71718 datasheet: Texas Instruments TPS5430 datasheet: FMC Specification Platform Management FRU Information Storage Definition V1.0 Avnet Electronics Marketing 4 of 19 Rev 1.0

5 2.0 Functional Description The DVI I/O FMC Module is a low pin count (LPC) FMC module containing interfaces intended for video processing. This module contains no processing intelligence and requires that it be plugged into a compatible baseboard for power, control and data processing. Figure 2 depicts the architecture of the FMC-DVI module. Subsequent sections provide details of the board design IPMI Identification I2C EEPROM (2 I2C) Video Clock Generation Video Clock Synth (2 GCLK) I2C Sub-System I2C MUX (3 I/O) I2C I/O Expander DVI Input DVI Input (1 GCLK, 27 I/O) FMC LPC Slot (68 I/O, 4 GCLK, 2 I2C, 1 GTP) DVI Output DVI Output (19 I/O) GPIO Header GPIO Header (10 I/O) DisplayPort Output Voltage Regulators 1-lane DisplayPort (5 I/O, 1 TX MGT) 1.8V Regulator FMC HPC Slot (xx I/O, x GCLK, x GTP) 4-lane DisplayPort (3 TX MGTs) 5.0V Regulator Figure 2 DVI I/O FMC Module, Block Diagram Avnet Electronics Marketing 5 of 19 Rev 1.0

6 2.1 FMC The DVI I/O FMC Module is populated with a HPC FMC connector. However, only the signals that constitute the LPC subset of HPC (columns H,G,D,C) are used. The only exception to this is the 3 additional GTPs which will allow a HPC carrier to access a full 4 lane DisplayPort output interface. Table 2 shows the LPC subset of the FMC connector. Table 2 FMC LPC Pinout Note: column signals K, J, F, E in the above table are not used and should be connected to GND. Columns A & B are not normally part of an LPC slot, but are added here to route the 3 extra GTPs needed for DisplayPort. Avnet Electronics Marketing 6 of 19 Rev 1.0

7 The FMC pin allocation for the DVI I/O FMC Module is defined in Table 3. H G D C B A 1 - GND 1 PG_C2M GND 2 PRSNT_M2C_L 2 GND DP_ML0+ 3 GND 3 GND DP_ML0-4 VIDEO_CLK2 GND 4 GTB_CLK0+ GND 5 VIDEO_CLK1 GND 5 GTB_CLK0- GND 6 GND DP2_AUX+ 6 GND - 7 DP2_AUX+ DP2_AUX- 7 GND - 8 DP2_AUX- GND 8 DP1_AUX+ GND 9 GND DP1_HPD 9 DP1_AUX- GND 10 DP_HPD DP2_HPD 10 GND DP1_AUX+ 11 EXTIO_INT GND 11 TP1 DP1_AUX- 12 GND DP_AUX+ 12 TP2 GND 13 DP_AUX+ DP_AUX- 13 GND GND 14 DP_AUX- GND 14 MUX_SDA TP3 15 GND I2C_RST 15 MUX_SCL DVII_DE 16 DVII_HSYNC DVII_VSYNC 16 GND GND 17 DVII_D22 GND 17 DVII_D23 GND 18 GND DVII_D21 18 DVII_D20 DVII_D19 GND 19 DVII_D16 DVII_D17 19 GND DVII_D18 GND 20 DVII_D15 GND 20 DVII_CLK GND GTB_CLK1+ GND 21 GND DVII_D13 21 DVII_D11 GND GTB_CLK1- GND 22 DVII_D14 DVII_D12 22 GND DVII_D10 GND DP_ML1+ 23 DVII_D8 GND 23 DVII_D9 DVIO_CLK+ GND DP_ML1-24 GND DVII_D6 24 DVII_D4 GND GND 25 DVII_D7 DVII_D5 25 GND GND GND 26 DVII_D1 GND 26 DVII_D2 DVII_D3 DP_ML2+ 27 GND DVII_D0 27 DVIO_D11 DVIO_D10 DP_ML2-28 DVIO_D8 DVIO_D9 28 GND GND GND 29 DVIO_D7 GND 29 - GND GND 30 GND DVIO_D5 30 TDI SCL DP_ML3+ 31 DVIO_D6 DVIO_D4 31 TDO 1 SDA DP_ML3-32 DVIO_D3 GND 32 3P3VAUX GND GND 33 GND DVIO_D GND GND 34 DVIO_D2 DVIO_D GA0 35 DVIO_DE GND 35 GA1 12P0V 36 GND DVIO_VSYNC 36 3P3V GND 37 DVIO_HSYNC DVIO_RST# 37 GND 12P0V 38 DVIO_HPD GND 38 3P3V GND 39 GND 39 GND 3P3V 40 GND 40 3P3V GND Table 3 DVI I/O FMC Module, FMC Pinout 1 TDO is connected to TDI in order not to break the JTAG chain Avnet Electronics Marketing 7 of 19 Rev 1.0

8 2.2 Voltage Sources All voltages on the DVI I/O FMC Module are implemented using TI discrete power solutions. The following table lists all the voltage sources available on the DVI I/O FMC Module. Voltage Name Voltage Current Description Supplied by FMC connector 33VAUX 3.3 V Used by IPMI Identification prior to module power-up V 3.3 V 2.5 V or 3.3 V +12 V 12.0 V Used for all signals connected to FMC connector. Supplied by on-board voltage regulators +1.8 V 1.8 V 150 ma Used by CDCE913 clock synthesizer. Generated by TPS71718DCKRG4. +5 V 5.0 V? Used by DVI and DisplayPort connectors. Generated by TPS5430. Table 4 DVI I/O FMC Module, Voltage Sources Avnet Electronics Marketing 8 of 19 Rev 1.0

9 2.3 I2C Chain 1 IPMI Identification EEPROM The DVI I/O FMC Module implements two I2C chains. The first I2C chain is used to implement the IPMI identification for the FMC module. 3P3VAUX GA1 GA0 EEPROM SCL SDA PRSTN_M2C_L PG_C2M EN# VREF_A_M2C FMC LPC (CON100) Figure 3 IPMI Identification, Block Diagram Before the module is powered-up, the carrier must identify the FMC module. At this point, the main power to the module is off. Only the auxiliary 3.3 V power rail (3P3VAUX) is active. The carrier detects the presence of an FMC module by verifying that PRSTN_M2C_L is asserted low. It then queries the I2C EEPROM to discover which voltage is requested by the module for. The EEPROM for this module will support the following voltages: 2.5 V 3.3 V The carrier will power up the module by applying the requested voltage to. When the voltage is valid, the PG_C2M (ie. power good) will be asserted high. An inverted version of this signal is used to enable all the voltage level translators connected to. VREF_A_M2C is not used for this FMC module. Avnet Electronics Marketing 9 of 19 Rev 1.0

10 The address of the I2C EEPROM will be determined by the GA[0:1] signals driven by the carrier. Note: The GA[0:1] bits are incorrectly connected on the DVI I/O FMC Module (they are swapped). Table 5 describes the normal EEPROM address, and the actual EEPROM address for the DVI I/O FMC Module. GA[0:1] Normal FMC I2C EEPROM Address FMC-DVI I2C EEPROM Address 00 0xA0 0xA0 01 0xA2 0xA4 10 0xA4 0xA2 11 0xA6 0xA6 Table 5 IPMI Identification, I2C EEPROM Address The GA[0:1] swap error will only be a problem on FMC carriers which are using both GA[0:1]==01 and GA[0:1]==10. This case does not exist in the current portfolio of FMC carriers, listed in Table 6. GA[0:1] mapping FMC Carrier FMC slot 1 FMC slot 2 Avnet Virtex-6 LX130T development kit 00b Avnet Spartan-6 LX150T development kit 00b 01b Avnet Spartan-6 LX16 low cost 00b Avnet Spartan-6 LX45T co-processing kit 00b Xilinx ML605 00b 01b Xilinx SP601 10b Xilinx SP605 10b Table 6 IPMI Identification, GA[0:1] mapping for FMC carriers The EEPROM content is defined by the Platform Management FRU Information Storage Definition V For the FMC-DVI module, the content is described in Table 7. Content DVI I/O FMC Module Board Information - Manufacturer Date/Time - - Manufacturer Avnet - Product FMC-DVI/DP - Serial - - Part Number AES-FMC-DVI-G - FRU File ID - Table 7 IPMI Identification, EEPROM Content Avnet Electronics Marketing 10 of 19 Rev 1.0

11 2.4 I2C Chain 2 Peripheral Configuration The DVI I/O FMC Module implements two I2C chains. The second I2C chain is used to configure the FMC module s peripherals. +5V 2 DVIO_SCL DVIO_SDA DDC EDID off-board devices MUX_SCL MUX_SDA 1 DVII_SCL DVII_SDA +5V DDC EDID I2C_SW_RST +3.3V 4 DEV_CLK_SCL DEV_CLK_SDA +3.3V Clock Synth. on-board devices 3 DEV_DVI_SCL DEV_DVI_SDA TMDS Serializer FMC LPC (J1) I2C Multiplexer (PCA9546A) I2C I/O Expander Figure 4 I2C Peripheral Configuration, Block Diagram The Texas Instruments PCA9546A I2C Multiplexer performs two purposes: Voltage level translation (2.5 V, 3.3 V, 5.0 V) I2C address conflict resolution The following table lists the I2C addresses that may be present on each of the I2C Multiplexer s ports. Notice that the I2C Multiplexer s address is always visible regardless of which port is enabled. Device I2C Multiplexer DVI Input DDC EDID DVI Output DDC EDID TMDS serializer I2C I/O Expander Clock Synthesizer I2C Address 0xE0 (PCA9546) Mux Port 1 0xA0 Mux Port 2 0xA0 / 0xA2 / 0xA6 Mux Port 3 0x70 (TFP410) 0x40 (PCA9555) Mux Port 4 0xCA (CDCE913) Table 8 I2C Peripheral Configuration, Device Summary Avnet Electronics Marketing 11 of 19 Rev 1.0

12 2.5 Video Clock Synthesizer A Video Clock Generator is included on the FMC module in order to provide a clock for all video applications. The following block diagram illustrates the connections for the Video Clock Generator. +1.8V +1.8V VDDout S0 +3.3V CLK1_M2C_P CLK1_M2C_N Y1 Y2 DEV_CLK_SCL DEV_CLK_SDA Y3 27 MHz FMC LPC (CON100) Video Clock Synthesizer (CDCE913) Figure 5 Video Clock Synthesizer, Block Diagram The Texas Instruments CDCE913 clock synthesizer has three clock outputs which are used as follows. Clock PLL Description Y1 PLL1 Can be used for any application Y2 PLL1 Can be used for any application Y3 - Unused Table 9 Video Clock Generator, Clock Output Usage The Y1 and Y2 clock outputs can be used for any application. One of these applications could be the clock source for the DVI output. The default mode of the CDCE913 is to output a 27 MHz clock on all of its outputs. Configuration is performed via I2C. The SDA/SCL pins of the CDCE913 device are 3.3 V tolerant. The settings of the CDCE913 video clock synthesizer can be calculated automatically using the TI Pro-Clock software. Avnet Electronics Marketing 12 of 19 Rev 1.0

13 2.6 DVI Input The DVI Input interface is implemented using the Texas Instruments TFP403 TMDS Deserializer. This device will only support a DVI compatible input signal. The reason for using an HDMI connector is only to same limited space. The following block diagram illustrates the connections between the FMC connector and TMDS Deserializer. +3.3V +3.3V DEV_DVI_SCL DEV_DVI_SDA CLK0_M2C_P DVII_CLK +5V DVII_VSYNC DVII_RXC+ DVII_RXC- +5V DVII_HSYNC DVII_DE DVII_RX[2:0]+ DVII_RX[2:0]- DVII_SCL DVII_SDA DVII_D[23:0] HDMI (J2) EEPROM DVII_PDO DVII_SCDT DVII_ST I2C I/O Expander DVII_CLKINV FMC LPC (J1) Voltage Level Translator (SN74AVC20T245) TMDS Deserializer (TFP403) (PCA9555) Figure 6 DVI Input, Block Diagram Avnet Electronics Marketing 13 of 19 Rev 1.0

14 2.7 DVI Output The DVI Output interface is implemented using the Texas Instruments TFP410 TMDS Serializer. This device generates a DVI compatible output signal which is sent to an HDMI connector. Since HDMI monitors are capable of displaying DVI signals, this output can be used to drive: DVI monitor (using a HDMI to DVI cable) HDMI monitor (using an HDMI cable) The following block diagram illustrates the connections between the FMC connector and TMDS Serializer. +3.3V +3.3V DVIO_TXC+ DVIO_TXC- DVIO_IDCK+ DVIO_IDCK- DVIO_RST# DVIO_VSYNC DVIO_HSYNC DVIO_DE DVIO_D[11:0] DEV_DVI_SCL DEV_DVI_SDA DVIO_TX[2:0]+ DVIO_TX[2:0]- +5V +5V DVIO_SCL DVIO_SDA Voltage Level Translator (SN74AVC20T245) TMDS Serializer (TFP410) HDMI (J3) DVIO_HPD HDMI_HOTPLUG FMC LPC (J1) Voltage Level Translator (SN74CB3T1G125) Figure 7 DVI Output, Block Diagram Avnet Electronics Marketing 14 of 19 Rev 1.0

15 2.8 DisplayPort Output The DisplayPort Output interface consists of some protective circuitry and a connector. Although a full 4-lane DisplayPort will be implemented, the two modes will be available depending on the carrier board: FMC LPC carrier board supporting MGT connections => 1 lane DisplayPort FMC LPC+ carrier board supporting 4 MGT connections => 4 lane DisplayPort FMC HPC carrier board supporting 4 MGT connections => 4 lane DisplayPort The DisplayPort will operate at one of the following data rates: 1.62 Gbps 2.6 Gbps The following block diagram illustrates the connections between the FMC connector and DisplayPort Output connector. +5V PG_C2M DP_HDP 27 MHz RST DP_REFCLK0+ FMC LPC pins available on all carriers Voltage Level Translator (SN74CB3T1G125) I2C I/O Expander (PCA9555) OS[1:0] PR[1:0] OD[2:0] Ultra Low jitter Clock Generator (CDCM61002) DP_ML1+ DP_ML1- DP_ML2+ DP_ML2- DP_ML3+ DP_ML3- DP_AUX+ DP_AUX- DP_REFCLK0- DP_REFCLK1+ DP_REFCLK1- FMC HPC pins available on some carriers DP_ML0+ DP_ML0- FMC LPC/HPC (J1) Protective Circuitry (TPD4E001, TPD8S009) DisplayPort (J4) Figure 8 DisplayPort Output, Block Diagram The Texas Instruments CDCM61002 ultra low jitter clock generator is used to generate the reference clocks for the DisplayPort s MGT transceivers. The DisplayPort IP core requires one of the following two reference clocks: 108 MHz 135 MHz The following table describes how to configure the CDCM61002 device to generate these two reference clocks. Input Clock Prescaler Divider Output Clock OS[1:0] PR[1:0] OD[2:0] 27 MHz * 24 / MHz MHz * 20 / MHz Table 10 DisplayPort Output, CDCM61002 Configuration Options Avnet Electronics Marketing 15 of 19 Rev 1.0

16 2.9 GPIO A general-purpose header will be provided for user specific functionality. The following block diagram illustrates the details of the GPIO header. +5V PG_C2M PWR GPIO_HPD1 GPIO_HPD2 Voltage Level Translator (? ) HPD1 HPD2 5V Single-Ended 5V Single-Ended GPIO_AUX1+ GPIO_AUX2- GPIO_AUX1- AUX1_P AUX1_N Bidirectionnal LVDS (1 Mbps) GPIO_AUX2+ AUX2_P AUX2_N Bidirectionnal LVDS (1 Mbps) FMC LPC (J1) GPIO Header (H1) Figure 9 GPIO, Block Diagram Avnet Electronics Marketing 16 of 19 Rev 1.0

17 One of the intended uses for the GPIO header is for the PCIe to DisplayPort adapter board. This adapter board provides the following signals from the PCIe connector: 4 lane DisplayPort output interface 4 lane DisplayPort input interface However, it is missing the Aux Channel and Hot Plug Detect signals. This header will provide the necessary number of signals to implement these, as illustrated in the following figure. Figure 10 GPIO, PCIe to DisplayPort adapter board (Use Case) Note: The PCIe to DisplayPort adapter board is presented as a use case only. Avnet does not commit to making this adapter. Avnet Electronics Marketing 17 of 19 Rev 1.0

18 3.0 Known Issues & Limitations This section describes the known issues and limitations for the DVI I/O FMC Module. 3.1 PG_C2M The FMC specification specified that a pull-up may be used on a FMC carrier for the C2M_PG signal. The DVI I/O FMC Module schematics, however, has a pull-down (R39) on this signal. This creates contention with the pull-up on the FMC carrier. This is a design error, and should not be copied to a new design. This error has been handled by not populating the components shown in the following figure. Figure 11 FMC-DVI, PG_C2M related components (R39 unpopulated) 3.2 GA[0:1] The FMC specification specified that the GA[0:1] signals should be connected to the IPMI EEPROM s A[1:0] address lines as follows: GA[0] => I2C EEPROM device s A[1] GA[1] => I2C EEPROM device s A[0] The FMC-IMAGEOV schematics, however, has the GA[0:1] connected in reverse order. GA[0] => I2C EEPROM device s A[0] GA[1] => I2C EEPROM device s A[1] This is a design error, and should not be copied to a new design. This error has not been fixed on the module since it can be handled by software. For more information on how this affects the address of the I2C EEPROM, refer to section I2C Chain 1 IPMI Identification EEPROM. Avnet Electronics Marketing 18 of 19 Rev 1.0

19 4.0 Revisions V1.0 Initial release for production board (AES-FMC-DVI-G Revision A) April 10, 2010 Avnet Electronics Marketing 19 of 19 Rev 1.0