A Survey on NAND Flash Memory Controller Using FPGA

Transcription

1 A Survey on NAND Flash Memory Controller Using FPGA Vijay Kumar Magraiya 1,Koushel Agarwal 2 Assistant Professor,SRCEM Gwalior, vijay.magraiya@gmail.com Research Scholar,SRCEM, Gwalior, Koushel_agarwal@yahoo.co.in Abstract-NAND flash memory is a non volatile storage media used in today daily life electronic equipments like cell phones, digital cameras, MP-3 players, PC etc. By experiments it is prove that high performance NAND flash controller can improve the data access performance in both program and read state drastically. As the cell size of NAND flash memory is reduced every year the performance, reliability, speed is increased very rapidly. NAND flash memory is programmed on page by page basis. Typically programming time is very less few micro second per page. A good ECC (Error correction code) technique is always essential in NAND flash memory controller. ECC can be implemented by both software and hardware. Good bad block management software is also essential to remap data to avoid using bad blocks in the memory device. A special Boot upcode is also written in the NAND flash memory controller so system can boot through it. It is a capacity Solid State Drive (SSD) that uses NAND flash memory for storage media in personal computer and enterprise server. Garbage Collector (GC) technique, Built in defect management technique, wear leaving technique is also used in NAND flash memory controller. We design and implement FPGA based open framework for fast, correct features of flash memories. Index Terms-Flash memory, Non volatile, Solid State Drive (SSD), Error Correction Code (ECC), Boot up code, Garbage Collector (GC), Defect management technique, Wear leaving technique, FPGA. 1. Introduction NAND flash memory is widely used in semiconductor industry for its high performance, low cost, high capacity, high speed, and low power consumption solid state data storage drive. Flash memory is the combination of two technologies-eprom and EEPROM. The term Flash means - A large chunk of memory (memory cell) could be erased at one time.on the other hand in EEPROM each byte is erased one by one manner. Traditional hard disk drive is now replaced by flash memory because flash memory is always good in all the above parameters. To improve the input output bandwidth we have a multi Chanel parallel access mechanism in the flash array. Each NAND flash memory controller has always an ECC and GC mechanism.it is very essential for security and performance point of view. Flash memory controller offers higher capacity for ShriRam College of Engineering & Management 1

2 fast data transfer and random access of memory in I/O operations. It is possible to design a simple memory mapped interface to hardware with NAND flash memory. NAND flash memory controller has also a bidirectional bus in between peripheral devices and controller, controller internal bus for various l functional blocks and controller with memory connections. These buses travel all the I/O data as well as control and address signals from one place to another. In NAND flash memory cell are arranged in series with sharing of source and drain, simply NMOS transistors are arranged for building NAND gate. So sharing the source and drain of adjacent cells eliminate need for metal contact and reduce the die size. NAND flash cells placed together for saving 60% cell size over NOR flash cells. In nor flash cells arrange in parallel with all source node of the cells connected as a NMOS transistors are arranged for building NOR gate. NAND flash memory controller provides a serial access of data blocks in a very high speed. Single Level Cell (SLC) and Multi Level Cell (MLC) two techniques are used for storing data in memory cells. SLC offers 100,000 erase program cycle while MLC offers about 10,000 erase program cycle. In MLC we require 4 bit ECC while in SLC we require only 1 bit ECC. So in NAND flash memory controller it essential whether we use SLC or MLC in appropriate ECC scheme. Open NAND Flash Interface (ONFI) provides a common standard for different devices. NAND flash memory devices generally have 512 bytes or 2048 bytes of data page with spare columns of 16 or 64 bits of extra data associated with each page for improvement data integrity and ECC purposes. System can also boot from the NAND flash memory by using BOOT ROM part and this BOOT UP code present in NAND flash memory. 2. NAND Flash Device Architecture In NAND flash device we have mainly three blocks- I/o control block, control logic NAND flash array. A NAND flash array includes two dimensional NAND flash cells, Row/Column address decoder and cache / data registers. In conventional NAND flash cell array read/program commands access data within single page at a time. In NAND flash device it have two data and cache registers to parallelize array and I/O access operations for good performance, command, address and data are controlled by I/O control block. It have a shared, multiplexed, bidirectional (command, address and data) I/O bus. Figure-1 shows the block diagram of a typical NAND flash device. The capacity of NAND flash device is improved day by day, architecture are also improved day by day. Latest overall structure of NAND flash device is looks very similar to its conventional structure. A NAND flash controller implements memory mapped interface. The logic block have two control logic-timing control logic block, control signal control logic block.a multiplane array packs contains its own set of Cache/Data registers, more memory cells on a die and partitioned it into several plans. In multiplane array packs all operations performs parallels. Inside a single flash array operation time multiple page of data can be programmed, read, write, fetched etc. so average data access time is small. In ShriRam College of Engineering & Management 2

3 multiplane commands some addresses are restricted. A multidie array packs have multiple dies on one chip. All are independent in operations and share a common data, address and command bus. So page programmed event, page erase event, command through the chip level I/O interface event are performed parallels with in a chip.so new NAND flash chip with multidie and multiplane support is always increase performance, reduce the data access average time, and increase parallel execution of commands. Fig 1:- Functional block diagram of a typical NAND flash device Conventional NAND Flash Controller- Conventional NAND flash controller have flash chips. In today life it is widely used in storage devices. At many applications it is a very good replacement of hard disk drive because its low cost, high performance, low power consumption etc. NAND flash controller receives data and commands signals from computer and translates it into a set of commands to flash chips. The address translation unit translates a logical address into a physical address for flash memory cell. Bad block management technique keeps track of damaged blocks. ECC unit checks errors and correct it so data integrity is managed. All the commands inside the controller follow a queue algorithm. It works on First In First Out(FIFO) concept. A conventional NAND flash controller is good in the field of area and data flow control. But it does not provide a high command level parallelisms and high performance. Proposed NAND Flash Controller-In my proposed controller we have following blocks-control logic block, registers, buffer, bidirectional bus for data, address and control signal, a high performance ECC interface, garbage collection mechanism, flash translation layered. It always follows Open NAND Flash Interface (ONFI) slandered. NAND flash devices are programmed on a page by page basis. Typically ShriRam College of Engineering & Management 3

4 programming time is a few hundred micro second per page. We use two plane programming cache programming and random programming. ONFI provides a common standard for different flash devices. So future extension and interfacing is possible and it is very easy. We also use some spare columns with each page. It is fully addressable and it is used for storing ECC and other information for improve data integrity. By using ECC we recover wrong value from the remaining good data bits. Each and every vendor use ECC in NAND flash applications. Flash controller generates ECC code, it store in spare column area. some remapping technique of logical to physical address of the memory device. A software called Flash Transaction layer (FTL) use for wear leveling and bad block management technique. All vendors provide FTL software. We also design improved FTL software in flash memory controller. We used some shadowing technique for improve the performance. A special boot up code is also developed to the first page of flash memory so CPU can boot from this page. All the initial instructions are written within this boot up page. So CPU can boot through NAND flash memory. NAND flash device declare some blocks as bad blocks. During production, testing, wafer fabrication steps each and every die is tested and bad blocks are marked. User always avoids use of bad blocks. Some additional bad blocks may develop due to use of memory again and again. So important to remap these bad blocks and marked it as a bad blocks so user can avoid it. NAND flash cell can be programmed and erased only for limited time period (100,000 times for SLC and 10,000 times for MLC) before it fails. We always want to improve this limitation so flash memory performance is increased. By using wear leveling technique we can achieve it. This technique spreads the memory cell use evenly to different physical pages. So the entire flash device is used equally to improve the life of flash memory. Bad block management technique and wear leveling technique use 3. SIMULATION RESULT ShriRam College of Engineering & Management 4

5 The testing the NAND interface with the FPGA device model was performed similar to the AMD UltraNAND device. The following commands were executed with the Denali model in modelsim with the test bench provided. Frame Program and Status Read are used to program a frame; The Frame Register must be loaded with data prior to executing the frame program command. The test bench provided loads the frame register with 32 bytes of data. The status of the device is checked with the Status Read command. Figure 4. Test bench wave form of Nand flash controller The Figure 4 shows the completion of the page Program command. And also Notice that RY/BY# signal is asserted, representating that the flash device is busy with an operation. After the Page Program command is sent to the flash, a Read Status command is sent. The Read Status command is used to read the device status. When I/O6 is equal to 1, the device is ready for the next command. To check if an operation is successful, reading me /O0 will determine the pass/fail status. When I/O0 is equal to 0,the operation passed and when equal to 1, the operation failed. When port address is high the program operation is successful as shown in figure 4. Figure 3. Memory address Loder wave form of Nand flash controller.. ShriRam College of Engineering & Management 5

6 4. CONCLUSION In this paper we discuss various aspects of NAND flash memory controller. A conventional NAND flash memory controller is shown as well as a proposed NAND flash memory controller is also present. We believe that proposed architecturewill achieve a high performance, low cost, low power consumption memory system with a low cost. We also want to achieve replacement of conventional HDD to NAND flash memory. The experimental results demonstrate that proposed architecture can achieve better performancein various parameters. We also want to develop a new Flash Transaction Layer (FTL) in our controller. We include a new Garbage collection (GC) policy, Error Correction Code (ECC), Control Logic (CL) etc.they all provide an FPGA to facilitate the implementation of a wide range of NAND flash memory controller. Proposed architecture can be work with all the embedded computing system as a replacement of conventionalhard Disk Drive (HDD) with a very huge size of NAND flash memory. It will be a very fast and reliable system. REFFERENCES [1] L. Bouganim, B. J onsson, and P. Bonnet. uflip understanding flash IO patterns, In Int l Conf. on Innovative Data Systems Research (CIDR), [2] P. Huang, Y. Chang, T. Kuo, J. Hsieh, and M. Lin. The Behavior Analysis of Flash-Memory Storage Systems, In IEEE Symposium on Object Oriented Real-Time Distributed Computing, pages IEEE Computer Society, [3] Hynix Semiconductor, Intel Corporation, Micron Technology Inc., Numonyx, Phison Electronics Corp.,Sony Corp., and Spansion. Open NAND FlashInterface Specification, rev Available from Jan [4]Yu Chi, Erich F. Haratsch, Mark McCatney and Ken Mai FPGA-Based Solid State Drive Prototyping Platform In IEEE International Symposium on Field Programmable Custom Computing Machines [5] Yang Ou, Nong Xiao and Mingche Lai A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture, Sixth Annual ChinaGrid Conference [6] International Technology Roadmap for Semiconductor, [7] Micron Technology, Boise, Idaho. Technical Note TN Design and Use Considerations for NAND Flash Memory, [8] Altera Corporation, Stratix data i sheet, May [9] Intel Corp., Understanding the Flash Transfer Layer (FTL) Specification, ShriRam College of Engineering & Management 6