Designing with External Flash Memory on Renesas Platforms

Transcription

1 Designing with External Flash Memory on Renesas Platforms Douglas Crane, Segment Manager Micron Technology Class ID: CL23A Renesas Electronics America Inc.

2 Douglas Crane Doug is a 27 year veteran in the electronics field. He currently works for Micron Technology as a Sr. Segment Manager driving application strategies, enabling the memory sub-system ecosystem and identifying roadmap requirements for embedded solutions group. Doug has been in the memory business for 16 years, 6 of which is with Micron and 10 with Toshiba in technical marketing roles for memory products. Prior to his memory experience, he spent 11 years involved in systems engineering at McDonnell Douglas and Rockwell. Doug has a BS in Applied Physics from University of California Irvine, MSEE from Cal State Fullerton, and an MBA from the University of Southern California. Doug has been involved in memory standards committee of JEDEC as well as been in the JEDEC board of directors 2

3 Renesas Technology & Solution Portfolio 3

4 Agenda Market Trends System Considerations Flash Cell Architectures RX62N PCM Demo Flash Memory Choices Summary 4

5 2012 Semiconductor Market Forecast Source: Gartner 3Q11 5

6 xram xram Memory/Bus Controller Memory/Bus Controller NAND Code copied and fixed in place at boot Flash NOR Memory Subsystem Designs/Architecture Execute in Place (XIP) Architecture Store and Download (SnD) Architecture Code Boot Flash xram MCU I$ D$ Data Flash xram MCU I$ D$ Data & Files Working Working Shadow Static Working Static Simple architecture Possible to reduce xram density Lower stand-by power Complex but higher performance More xram required Higher stand-by power 6

7 Platform Memory Mapping Platform Internal Flash SNOR External Flash Memory PNOR Managed NAND RH850 V K-8MB 16KB-2MB x32 X8/ x16 SoC RX 32K-2MB 128Mb SuperH SH2/2A 16K-2MB SH4/4A X H8SX 128K-1MB RL78 2KB-512KB 8Mb R Car H1 X emmc R Car M1x X emmc 7

8 System Cost Reductions and Simplification Software Architecture System Architecture N+3 High Write CPU Main Memory RAM NVM N+2 N+1 N Critical Data Shadowed Code High Read Boot Code + OS Memory Banks Complimentary I/O E 2 BatRAM/nvRAM NOR/NAND Understand your usage model xram usage models How many CE#/banks do you use Why might you split memory into separate chips Other system SW requirements (file system, data logging, etc) System BOM Can you eliminate or partially eliminate any unnecessary memory? Performance vs. Cost ratio 8

9 Larger Data Fetches 9

10 Performance Comparison Small Data 10

11 Cell Architectures Floating Gate Technologies S/D Polysilicon Gate Oxide Nitride Oxide S/D Electron Storage S Polysilicon Gate ONO Polysilicon Oxide D PCM Technology Temperature T m T x Reset (amorphization) Set (crystallization) Time 11

12 PCM Benefits Bit alterability Scaling No erase required & 45nm today 5nm future Endurance Bit Errors 12

13 Hardware Setup Renesas RX62N development board Embedded components: RX62N microcontroller Micron SPI (P5Q) Additional components Micron SPI (M25P) 128Mb NOR SPI (M25P) USB use for power only Computes Electrical outlet arrow up button arrow down button Enter enter button 128Mb PCM SPI (P5Q) 13

14 Micron/Renesas Software Comparing NOR vs PCM NOR SPI Industry erase & program PCM SPI Industry erase & program PCM specific commands Data outputted Erase time Program time Assumptions: Image size (2-Mbytes) Clock frequency (30-MHz) Single I/O Choosing NOR (M25P) Program Method Output data Choosing PCM (P5Q) Erase time = Seconds Program time = Seconds 14

15 Experiment #1 NOR vs. PCM Product background: Product Frequency Erase Size Program Size Program Command Cycles M25P 50MHz 2Mb 256 Bytes 02h 100,000 P5Q 66MHz 1Mb 64 Bytes 02h 1,000,000 Data collected: SF PMOD (M25P16) Erase Before Program SF2 PMOD (P5Q128) Erase Before Program Variables Image size, SPI mode & frequency Lessons learned: 3x improvement with minimal software changes 15

16 What is Program on All 1 s 02h Floating Gate Program D1h PCM Program on ALL 1 s Erase Block Program Data Erase Block Program Data 16

17 Experiment #2 Program on All 1 s Product background: Product Frequency Erase Size Program Size Program Command Cycles M25P 50MHz 2Mb 256 Bytes 02h 100,000 P5Q 66MHz 1Mb 64 Bytes D1h 1,000,000 Data collected: SF PMOD (M25P16) Erase Before Program SF2 PMOD (P5Q128) Program on All 1 s Variables Image size, SPI mode & frequency Lessons learned: D1h is a smaller software change than 22h to get 4x improvement In-system program command can be used to improve performance 17

18 What is Bit Alterable Write 02H Floating Gate Program 22h PCM Bit Alterable Write X NO! Erase Block YES! Bit Alterable Write Program Data Faster performance Easier data manipulation 18

19 Experiment #3 Bit Alterable Write Product background: Product Frequency Erase Size Program Size Program Command Cycles M25P 50MHz 2Mb 256 Bytes 02h 100,000 P5Q 66MHz 128Kb 64 Bytes 22h 1,000,000 Data collected: SF PMOD (M25P16) Erase Before Program SF2 PMOD (P5Q128) Bit Alterable Variables Image size, SPI mode & frequency Lessons learned: PCM Bit alterability improves performance by 10x 19

20 Experiment #4 Test Your Endurance Product background: *Definition of Cycle: Floating Gate vs. PCM* Product Frequency Erase Size Program Size Program Command Cycles M25P 50MHz 2Mb 256 Bytes 02h 100,000 P5Q 66MHz 128Kb 64 Bytes 02h or 22h 1,000,000 Data collected: SF2 PMOD (P5Q128) Erase Before Program or Bit Alterable SF PMOD (M25P16) Erase Before Program Variables Image size, SPI mode & frequency Lessons learned: PCM offers 10x endurance vs. NOR 20

21 Seconds Seconds Seconds Data Summary & Brainstorming NOR vs PCM... Erase Before Write 35 NOR vs PCM... Program on All 1's x Faster Erase Program Verify x Faster Erase Program Verify Total Time PCM Erase Before Write NOR Erase Before Write 0 PCM Erase Before Write PCM Program on All 1's NOR Erase Before Write 35 NOR vs PCM... Bit Alterable x Faster Erase Program Verify Total Time 0 PCM Bit Alterable Write PCM Program on All 1's PCM Erase Before Write NOR Erase Before Write What application would PCM go into today 21

22 Your Own Development Board Link here to get your board or talk to your Renesas representative 22

23 Solutions for Different Requirements NOR vs. NAND Lowest Floor Cost ($) Lowest $/GB Serial NOR Parallel NOR SLC NAND Managed NAND MLC NAND Longer lifecycles Ease of use Diverse products Lower Floor cost Code, Code+Data Shorter lifecycles Focus on cost/gb Expanding markets Mostly Data Focused Customer requirements dictate the solution 23

24 NOR Product Attributes Simple command sets Cost effective at low densities Stable architectures Value added features (XiP, security, quality, small data, etc) Serial Low pin counts Easy PCB routing Smallest footprint Synchronous operations Cheapest low density Parallel Basic add/data interface Asynchronous random access Synchronous burst operations Higher throughput Best XiP architecture 24

25 NAND Product Attributes Low pin counts Cheapest cost/bit at high densities Frequent conversions/migrations required Fast programming Discrete Some controllers support boot Some standards (ONFI) Common packages Needs SW for error management Demand paging saves bits Managed Error management onboard Some controllers support boot Higher density reach Easier conversions/migrations Standards (MMC, USB, usd ) 25

26 Flash Architectures Component Level All architectures have their advantages Trend in the industry moving toward the lower pin count architectures 26

27 NAND Technology Challenges How to manage the ECC requirements? NAND controllers with high ECC capability ECC NAND managed solutions on-die ECC, ClearNAND Fully managed solutions emmc, eusb, others How to manage lower endurance? Understand the application and usage model How does the file system work? How often are you programming? How big is the data file/s? What is the PLC of your system? Determines PE Cycles and density required Intersecting your project and the memory technology is key to success! 27

28 NAND System Solutions for Industry Raw NAND for application expert with NAND data management and ready to support ECC needs. Host Controller I NAND Interface FTL ECC LLD NAND BUS Raw NAND ECC NAND for application that do not want to change the ECC with the NAND litho shrink. Host Controller II NAND Interface FTL LLD NAND BUS ECC NAND ECC Serial NAND for application requiring high density with serial protocol. Host Controller III SPI Interface FTL LLD SPI BUS SPI ECC emmc interface for application that want to offload by any NAND data management with a standard interface. Host Controller IV emmc Interface LLD MMC BUS emmc NAND ECC FTL eusb interface for application that want to offload by any NAND data management with a standard interface. Host Controller V eusb Interface LLD USB BUS eusb NAND ECC FTL 28

29 Memory Technology Comparison Attributes PCM DRAM NAND NOR EEpROM Bit Alterable Non-volatile Cost Read Speed Write Speed All memory technologies have their advantages Look for ways to differentiate and stay cost effective 29

30 Summary Customer Next Steps 1. Understand memory usage 2. Understand true cost 3. Work with a trustworthy supplier Supplier Identification 1. Provides technology leadership & product longevity 2. Architecture transparency 3. Systems expertise & silicon/solution standards 30

31 Questions? 31

32 Please Provide Your Feedback Please utilize the Guidebook application to leave feedback or Ask me for the paper feedback form for you to use 32

33 Class ID: Renesas Electronics America Inc.