ECE 448 Lecture 13. FPGA Memories. George Mason University
|
|
|
- Jessie Golden
- 5 years ago
- Views:
Transcription
1 ECE 448 Lecture 13 FPGA Memories George Mason University
2 Recommended reading Spartan-6 FPGA Block RAM Resources: User Guide Google search: UG383 Spartan-6 FPGA Configurable Logic Block: User Guide Google search: UG384 Xilinx FPGA Embedded Memory Advantages: White Paper Google search: WP360 2
3 Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM HDL Coding Techniques ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module 3
4 Memory Types 4
5 Memory Types Memory RAM ROM Memory Single port Dual port Memory With asynchronous read With synchronous read 5
6 Memory Types specific to Xilinx FPGAs Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using CORE Generator 6
7 FPGA Distributed Memory 7
8 Location of Distributed RAM Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 8
9 Three Different Types of Slices 50% 25% 25% 9
10 Spartan-6 Multipurpose LUT (MLUT) 16-bit 32-bit SR x 1 RAM 4-input 64 x 1 ROM LUT (logic) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 10
11 Single-port 64 x 1-bit RAM 11
12 Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: Single-port 128 x 1-bit RAM: RAM128x1S Dual-port 64 x 1-bit RAM : RAM64x1D Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S Dual-port 128 x 1-bit RAM: RAM128x1D Quad-port 64 x 1-bit RAM: RAM64x1Q Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP (one address for read, one address for write) 12
13 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 13
14 Total Size of Distributed RAM 14
15 FPGA Block RAM 15
16 Location of Block RAMs Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 16
17 Spartan-6 Block RAM Amounts 17
18 Block RAM can have various configurations (port aspect ratios) k x 2 4k x 4 4,095 16k x 1 8, k x (8+1) 16, x (16+2) 18
19 19
20 20
21 Block RAM Port Aspect Ratios 21
22 Block RAM Interface 22
23 Block RAM Ports 23
24 Block RAM Waveforms READ_FIRST mode 24
25 Block RAM Waveforms WRITE_FIRST mode 25
26 Block RAM Waveforms NO_CHANGE mode 26
27 Features of Block RAMs in Spartan-6 FPGAs 27
28 Inference vs. Instantiation 28
29 29
30 Using CORE Generator 30
31 CORE Generator 31
32 CORE Generator 32
33 Generic Inferred ROM 33
34 Distributed ROM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Entity ROM is generic ( w : integer := 12; -- number of bits per ROM word r : integer := 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM; 34
35 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := (" ", " ", " ", " ", " ", " ", " ", " "); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral; 35
36 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("0C4", "4D2", "4DB", "6C2", "0F1", "7D6", "4D0", "F9F"); begin dout <= ROM_array(conv_integer(unsigned(addr))); end behavioral; 36
37 Generic Inferred RAM 37
38 Distributed versus Block RAM Inference Examples: 1. Distributed single-port RAM with asynchronous read 2. Distributed dual-port RAM with asynchronous read 3. Block RAM with synchronous read (no version with asynchronous read!) More excellent RAM examples from XST Coding Guidelines. 38
39 Distributed single-port RAM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 39
40 Distributed single-port RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral; 40
41 Distributed dual-port RAM with asynchronous read library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr; 41
42 Distributed dual-port RAM with asynchronous read architecture syn of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(conv_integer(unsigned(a))); dpo <= RAM(conv_integer(unsigned(dpra))); end syn; 42
43 Block RAM Waveforms READ_FIRST mode 43
44 Block RAM with synchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 44
45 Block RAM with synchronous read Read-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then do <= RAM(conv_integer(unsigned(addr))); if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; end if; end if; end if; end process; end behavioral; 45
46 Block RAM Waveforms WRITE_FIRST mode 46
47 Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 47
48 Block RAM Waveforms NO_CHANGE mode 48
49 Block RAM with synchronous read No-Change Mode - cont'd architecture behavioral of raminfr is type ram_type is array (2**r-1 downto 0) of std_logic_vector (w-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(unsigned(addr))) <= di; else do <= RAM(conv_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 49
50 Criteria for Implementing Inferred RAM in BRAMs 50
ECE 545 Lecture 17 RAM. George Mason University
ECE 545 Lecture 17 RAM George Mason University Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques [ UG687 (v 14.5) March 20, 2013 ] Sections:
ECE 699: Lecture 9. Programmable Logic Memories
ECE 699: Lecture 9 Programmable Logic Memories Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM
ECE 545: Lecture 11. Programmable Logic Memories
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Memory Resources:
ECE 545: Lecture 11. Programmable Logic Memories. Recommended reading. Memory Types. Memory Types. Memory Types specific to Xilinx FPGAs
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Resources: User
Lecture 11 Memories in Xilinx FPGAs
Lecture 11 Memories in Xilinx FPGAs ECE 448 FPGA and ASIC Design with VHDL Recommended reading XAPP463 Using Block RAM in Spartan-3 Generation FPGAs Google search: XAPP463 XAPP464 Using Look-Up Tables
CDA 4253 FGPA System Design Xilinx FPGA Memories. Hao Zheng Comp Sci & Eng USF
CDA 4253 FGPA System Design Xilinx FPGA Memories Hao Zheng Comp Sci & Eng USF Xilinx 7-Series FPGA Architecture On-Chip block RAM On-Chip block RAM Distributed RAM by Logic Fabric Distributed RAM by Logic
ECE 545 Lecture 12. FPGA Embedded Resources 12/8/11. Resources. Recommended reading. Use of Embedded FPGA Resources in SHA-3 Candidates
ECE 545 Lecture 12 FPGA Embedded Resources Resources FPGA Embedded Resources web page available from the course web page George Mason University 2 Recommended reading XAPP463 Using Block RAM in Spartan-3
ELE432. ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY ROUTING and FPGA MEMORY. In part from ECE 448 FPGA and ASIC Design with VHDL
ELE432 ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY ROUTING and FPGA MEMORY In part from ECE 448 FPGA and ASIC Design with VHDL Organization of the Week Routing in FPGA Memory Design in FPGA Xilinx Programmable
ECE 448 Lecture 5. FPGA Devices
ECE 448 Lecture 5 FPGA Devices George Mason University Required reading Spartan-6 FPGA Configurable Logic Block: User Guide CLB Overview Slice Description 2 Recommended reading Highly recommended for the
ECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
VHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2
VHDL: Modeling RAM and Register Files Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 Memory Synthesis Approaches: Random logic using flip-flops or latches Register files in datapaths RAM standard components
Block RAM. Size. Ports. Virtex-4 and older: 18Kb Virtex-5 and newer: 36Kb, can function as two 18Kb blocks
Block RAM Dedicated FPGA resource, separate columns from CLBs Designed to implement large (Kb) memories Multi-port capabilities Multi-clock capabilities FIFO capabilities Built-in error detection and correction
Hardware Design with VHDL Design Example: BRAM ECE 443
BRAM There are two sources of memory available on most FPGA boards. Internal (on-chip memory) External SRAMs and DRAMs. Internal memory is either distributed (from the LUTs) or block (dedicated on-chip
ECE 448 Lecture 5. FPGA Devices
E 448 Lecture 5 FPGA evices E 448 FPGA and ASIC esign with VHL George Mason University Required reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional etails 2 What is an FPGA?
CPE 626 Advanced VLSI Design Lecture 7: VHDL Synthesis
CPE 626 Lecture 7 VHDL Synthes Aleksar Milenkovic http//www.ece.uah.edu/~milenka http//www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Asstant Pressor Electrical Computer Engineering Dept. University
Midterm Exam. Solutions
Midterm Exam Solutions Problem 1 List at least 3 advantages of implementing selected portions of a complex design in software Software vs. Hardware Trade-offs Improve Performance Improve Energy Efficiency
Field Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 15 Memories
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 15 Memories 1 Overview Introduction Memories Read Only Memories Random Access Memories FIFOs 2 1 Motivation Most applications need memory!
Laboratory Memory Components
Laboratory 3 3. Memory Components 3.1 Objectives Design, implement and test Register File Read only Memories ROMs Random Access Memories RAMs Familiarize the students with Xilinx ISE WebPack Xilinx Synthesis
COVER SHEET: Total: Regrade Info: 2 (6 points) 3 (8 points) 4 (10 points) 8 (12 points) 6 (6 points) 7 (6 points) 9 (30 points) 10 (4 points)
EEL 4712 Midterm 2 Spring 2010 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University
ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential
ECE 645: Lecture 1. Basic Adders and Counters. Implementation of Adders in FPGAs
ECE 645: Lecture Basic Adders and Counters Implementation of Adders in FPGAs Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 5, Basic Addition and Counting,
ECEU530. Project Presentations. ECE U530 Digital Hardware Synthesis. Rest of Semester. Memory Structures
ECEU53 ECE U53 igital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 5, 26 Lecture 8: Student project presentations Memories and FPGAs Tri-state buffers and busses Student project presentations:
COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points)
EEL 4712 Midterm 2 Spring 2011 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
HDL Coding Style Xilinx, Inc. All Rights Reserved
HDL Coding Style Objective After completing this module, you will be able to: Select a proper coding style to create efficient FPGA designs Specify Xilinx resources that need to be instantiated for various
CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis. Register File: An Example. Register File: An Example (cont d) Aleksandar Milenkovic
CPE 626 Lecture 6: VHDL Synthesis Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and Computer Engineering
CprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
ECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University
ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design:
Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012
Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012 Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely
Timing in synchronous systems
BO 1 esign of sequential logic Outline Timing in synchronous networks Synchronous processes in VHL VHL-code that introduces latches andf flip-flops Initialization of registers Mealy- and Moore machines
FSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques
FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Built-in FSM encoding strategies to accommodate your optimization goals. You may also
ECEU530. Last Few Lectures. ECE U530 Digital Hardware Synthesis. What is on Quiz 2. Projects. Today:
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 29, 2006 Lecture 20: Review for Quiz Generics and Generate Functions and Procedures Memories Teaching Evaluations Quiz on
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
Digital System Construction
Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion
Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs
Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs UG768 (v14.7) October 2, 2013 tice of Disclaimer The information disclosed to you hereunder (the "Materials") is
Vivado Design Suite 7 Series FPGA Libraries Guide. UG953 (v ) July 25, 2012
Vivado Design Suite 7 Series FPGA Libraries Guide UG953 (v 2012.2) July 25, 2012 tice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and
Programmable Logic. Simple Programmable Logic Devices
Programmable Logic SM098 Computation Structures - Programmable Logic Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements
ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
EECS150 - Digital Design Lecture 16 - Memory
EECS150 - Digital Design Lecture 16 - Memory October 17, 2002 John Wawrzynek Fall 2002 EECS150 - Lec16-mem1 Page 1 Memory Basics Uses: data & program storage general purpose registers buffering table lookups
Lecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
ECE 545 Lecture 4. Simple Testbenches. George Mason University
ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench
Experiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003
Experiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003 On my honor I have neither received nor given aid on this report. Signed: Ronald J. Hayne Part I Description of the Experiment Experiment
Spartan-6 Libraries Guide for HDL Designs. UG615 (v 13.1) March 1, 2011
Spartan-6 Libraries Guide for HDL Designs UG615 (v 13.1) March 1, 2011 Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the
The Virtex FPGA and Introduction to design techniques
The Virtex FPGA and Introduction to design techniques SM098 Computation Structures Lecture 6 Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL
The VHDL Hardware Description Language
The VHDL Hardware Description Language p. 1/? The VHDL Hardware Description Language CSEE W4840 Prof. Stephen A. Edwards Columbia University The VHDL Hardware Description Language p. 2/? Why HDLs? 1970s:
Basic FPGA Architecture Xilinx, Inc. All Rights Reserved
Basic FPGA Architecture 2005 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Identify the basic architectural resources of the Virtex -II FPGA List the differences
Sequential Logic - Module 5
Sequential Logic Module 5 Jim Duckworth, WPI 1 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the
ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles
ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended
Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide. UG953 (v2014.2) June 4, 2014
Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide Chapter 1 Introduction Overview This HDL guide is part of the Vivado Design Suite documentation collection. This guide
Implementation of Directional Median Filtering using Field Programmable Gate Arrays
University of New Orleans ScholarWorks@UNO University of New Orleans Theses and Dissertations Dissertations and Theses 12-17-2010 Implementation of Directional Median Filtering using Field Programmable
Digital Design Laboratory Lecture 2
ECE 280 / CSE 280 Digital Design Laboratory Lecture 2 Adder Design Basic building block is a full adder Chained together as a ripple carry adder Carry lookahead adder is an other option Propagate and generate
Spartan-6 Libraries Guide for HDL Designs. UG615 (v 14.1) April 24, 2012
Spartan-6 Libraries Guide for HDL Designs UG615 (v 14.1) April 24, 2012 tice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx
EECS150 - Digital Design Lecture 16 Memory 1
EECS150 - Digital Design Lecture 16 Memory 1 March 13, 2003 John Wawrzynek Spring 2003 EECS150 - Lec16-mem1 Page 1 Memory Basics Uses: Whenever a large collection of state elements is required. data &
VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents
VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
FPGA design with National Instuments
FPGA design with National Instuments Rémi DA SILVA Systems Engineer - Embedded and Data Acquisition Systems - MED Region ni.com The NI Approach to Flexible Hardware Processor Real-time OS Application software
Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
ECE 448 FPGA and ASIC Design with VHDL. Spring 2018
ECE 448 FPGA and ASIC Design with VHDL Spring 2018 Kris Gaj Research and teaching interests: reconfigurable computing cryptography computer arithmetic network security Contact: The Engineering Building,
CDA 4253 FPGA System Design Op7miza7on Techniques. Hao Zheng Comp S ci & Eng Univ of South Florida
CDA 4253 FPGA System Design Op7miza7on Techniques Hao Zheng Comp S ci & Eng Univ of South Florida 1 Extracted from Advanced FPGA Design by Steve Kilts 2 Op7miza7on for Performance 3 Performance Defini7ons
FPGA Lecture for LUPO and GTO Vol , 31 August (revised 2013, 19 November) H. Baba
FPGA Lecture for LUPO and GTO Vol. 1 2010, 31 August (revised 2013, 19 November) H. Baba Contents Basic feature of FPGA Basic usage for LUPO New project Read and Write Basic behavioral VHDL simulation
Xilinx ASMBL Architecture
FPGA Structure Xilinx ASMBL Architecture Design Flow Synthesis: HDL to FPGA primitives Translate: FPGA Primitives to FPGA Slice components Map: Packing of Slice components into Slices, placement of Slices
Schedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 8, 2006 Midterm Average: 70 Lecture 16: Midterm Solutions Homework 6: Calculator Handshaking HW 6: Due Wednesday, November
FPGAs in a Nutshell - Introduction to Embedded Systems-
FPGAs in a Nutshell - Introduction to Embedded Systems- Dipl.- Ing. Falk Salewski Lehrstuhl Informatik RWTH Aachen salewski@informatik.rwth-aachen.de Winter term 6/7 Contents History FPGA architecture
Data Side OCM Bus v1.0 (v2.00b)
0 Data Side OCM Bus v1.0 (v2.00b) DS480 January 23, 2007 0 0 Introduction The DSOCM_V10 core is a data-side On-Chip Memory (OCM) bus interconnect core. The core connects the PowerPC 405 data-side OCM interface
Summary of FPGA & VHDL
FYS4220/9220 Summary of FPGA & VHDL Lecture #6 Jan Kenneth Bekkeng, University of Oslo - Department of Physics 16.11.2011 Curriculum (VHDL & FPGA part) Curriculum (Syllabus) defined by: Lectures Lecture6:
ECEU530. Schedule. ECE U530 Digital Hardware Synthesis. Datapath for the Calculator (HW 5) HW 5 Datapath Entity
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 6, 2006 Classes November 6 and 8 are in 429 Dana! Lecture 15: Homework 5: Datapath How to write a testbench for synchronous
CCE 3202 Advanced Digital System Design
CCE 3202 Advanced Digital System Design Lab Exercise #2 Introduction You will use Xilinx Webpack v9.1 to allow the synthesis and creation of VHDLbased designs. This lab will outline the steps necessary
ECE 545 Lecture 11 Addendum
ECE 545 Lecture 11 Addendum Controllers for Keccak_F and AES George Mason University ECE 448 FPGA and ASIC Design with VHDL Keccak_F 1600 din start done Keccak_F rst 1600 dout ready Note: Bold line represents
IP cores. V. Angelov
IP cores V. Angelov VHDL-FPGA@PI 2013 1 IP cores Soft IP cores Hard IP cores ROM, RAM, FIFO RISC CPU DSP - Multiplier SerDes Flash memory (boot, user) PCI, PCIe JTAG V. Angelov VHDL-FPGA@PI 2013 2 Soft
Reconfigurable Hardware Design (coursework)
EEE8076 Reconfigurable Hardware Design (coursework) Dr A. Bystrov Dr. E.G. Chester Autumn 2010 Module Outline Teaching Staff Dr Alex Bystrov Dr Graeme Chester The contact details are in the EECE web page
Virtex-5 Libraries Guide for HDL Designs. UG621 (v 14.1) April 24, 2012
Virtex-5 Libraries Guide for HDL Designs UG621 (v 14.1) April 24, 2012 This document applies to the following software versions: ISE Design Suite 14.1 through 14.4 tice of Disclaimer The information disclosed
Assignment. Last time. Last time. ECE 4514 Digital Design II. Back to the big picture. Back to the big picture
Assignment Last time Project 4: Using synthesis tools Synplify Pro and Webpack Due 11/11 ning of class Generics Used to parameterize models E.g., Delay, bit width Configurations Configuration specification
Implementing Multipliers in Xilinx Virtex II FPGAs
HUNT ENGINEERING Chestnut Court, Burton Row, Brent Knoll, Somerset, TA9 4BP, UK Tel: (+44) (0)1278 760188, Fax: (+44) (0)1278 760199, Email: sales@hunteng.co.uk http://www.hunteng.co.uk http://www.hunt-dsp.com
ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. Behavioral Design Style: Registers & Counters.
ECE 55 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks Required reading P. Chu, RTL Hardware esign using VHL Chapter 5.1, VHL Process Chapter 8, Sequential Circuit esign: Principle
Lecture 5: Aldec Active-HDL Simulator
Lecture 5: Aldec Active-HDL Simulator 1. Objective The objective of this tutorial is to introduce you to Aldec s Active-HDL 9.1 Student Edition simulator by performing the following tasks on a 4-bit adder
Design Problem 5 Solutions
CS/EE 260 Digital Computers: Organization and Logical Design Design Problem 5 Solutions Jon Turner Due 5/4/04 1. (100 points) In this problem, you will implement a simple shared memory multiprocessor system
Digital Systems Design
Digital Systems Design Memory Implementation on Altera CYCLONE V Devices Electrical & Computer Engineering Dr. D. J. Jackson Lecture 6-1 Embedded Memory 10 Kb M10K blocks blocks of dedicated memory resources
Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Output Sum(4 bits) Adder. Output carry(1 bit)
Csc 343 Lab 2 Sep 28. 07 Objective: Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Structure: Input A (4 bits) Input B (4 bit) Adder Output Sum(4 bits) Output carry(1 bit) input cin
Sign here to give permission for your test to be returned in class, where others might see your score:
EEL 4712 Midterm 2 Spring 216 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
Sequential Statement
Sequential Statement Sequential Logic Output depends not only on current input values but also on previous input values. Are building blocks of; Counters Shift registers Memories Flip flops are basic sequential
Constructing VHDL Models with CSA
Constructing VHDL Models with CSA List all components (e.g., gate) inclusive propagation delays. Identify input/output signals as input/output ports. All remaining signals are internal signals. Identify
Use of Embedded FPGA Resources in Implementations of Five Round Three SHA-3 Candidates
Use of Embedded FPGA Resources in Implementations of Five Round Three SHA-3 Candidates Malik Umar Sharif, Rabia Shahid, Marcin Rogawski and Kris Gaj George Mason University, USA Agenda SHA-3 High Speed
Example 15: Moving Sprites with Flash Background
Displaying an Image Read from Flash Memory 95 Listing 2.5 (cont.) vga_flash_n2_top.vhd clr
Midterms Exam Fall 2011 Solu6ons
Midterms Exam Fall 2011 olu6ons olu6on to Task 1 m 0 1 sel0 a0_in a0 0 1 sel 2.5 points Datapath main iterate loop 0 1 sel 10 points 0 1 sel 0 1 sel 0 1 sel y=a0_out a0 en en0 en en a1 7.5 points a2 en
FPGA briefing Part II FPGA development DMW: FPGA development DMW:
FPGA briefing Part II FPGA development FPGA development 1 FPGA development FPGA development : Domain level analysis (Level 3). System level design (Level 2). Module level design (Level 1). Academical focus
Lab 4: Integrating a picoblaze processor in LabVIEW FPGA by use of CLIP node
Lab 4: Integrating a picoblaze processor in LabVIEW FPGA by use of CLIP node Keywords: LabVIEW, LabVIEW FPGA, Xilinx SPARTAN3E Starter Kit, VHDL, picoblaze, assembler, CLIP node. Introduction Welcome to
Design Guidelines for Using DSP Blocks
Design Guidelines for Using DSP Blocks in the Synplify Software April 2002, ver. 1.0 Application Note 193 Introduction Altera R Stratix TM devices have dedicated digital signal processing (DSP) blocks
EEE8076. Reconfigurable Hardware Design (coursework) Module Outline. Dr A. Bystrov Dr. E.G. Chester. Autumn
EEE8076 Reconfigurable Hardware Design (coursework) Module Outline Dr A. Bystrov Dr. E.G. Chester Autumn 2010 1 2 3 4 5 6 7 8 9 10 11 12 Altera UP2 development board, Flex EPF10K70 FPGA www.altera.com/literature/univ/upds.pdf
FPGA.
CMOS TTL Verilog VHDL mshora@yahoo.com 7400. NAND CMOS TTL 1 0 source sink datasheet bounce bounce debunce RS Latch debounce Typical Characteristics NO NC Semiconductor Material Wavelength Colour V F @
Writing VHDL for RTL Synthesis
Writing VHDL for RTL Synthesis Stephen A. Edwards, Columbia University December 21, 2009 The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSIC Hardware
entity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority;
Примери Приоритетен кодер library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority; architecture Behavioral
EE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Module 2 Eric Crabill SJSU / Xilinx Fall 2007 Lecture #4 Agenda Survey of implementation technologies. Implementation Technologies Small scale and medium scale integration. Up to about 200
Use of Embedded FPGA Resources in Implementa:ons of 14 Round 2 SHA- 3 Candidates
Use of Embedded FPGA Resources in Implementa:ons of 14 Round 2 SHA- 3 Candidates Kris Gaj, Rabia Shahid, Malik Umar Sharif, and Marcin Rogawski George Mason University U.S.A. Co-Authors Rabia Shahid Malik
EE261: Intro to Digital Design
2014 EE261: Intro to Digital Design Project 3: Four Bit Full Adder Abstract: This report serves to teach us, the students, about modeling logic and gives a chance to apply concepts from the course to a
EECS150 - Digital Design Lecture 13 - Project Description, Part 2: Memory Blocks. Project Overview
EECS150 - igital esign Lecture 13 - Project escription, Part 2: Memory Blocks Mar 2, 2010 John Wawrzynek Spring 2010 EECS150 - Lec13-proj2 Page 1 Project Overview A. MIPS150 pipeline structure B. Serial
Designing with VHDL and FPGA
Designing with VHDL and FPGA Instructor: Dr. Ahmad El-Banna lab# 5-II 1 Agenda Structural way in VHDL Mixed Example 2 Modeling the Structurural way Structural architecture implements the module as a composition
EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructor: John Wawrzynek. Lecture 18 EE141
EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructor: John Wawrzynek Lecture 18 Memory Blocks Multi-ported RAM Combining Memory blocks FIFOs FPGA memory blocks Memory block synthesis