I 2 C Serial EEPROM Family Data Sheet

Transcription

1 24AA00/24LC00/24C00 24AA01/24LC01B 24AA014/24LC014 24C01C 24AA02/24LC02B 24C02C 24AA024/24LC024 24AA025/24LC025 24AA04/24LC04B 24AA08/24LC08B 24AA16/24LC16B 24AA32A/24LC32A 24AA64/24LC64/24FC64 24AA128/24LC128/24FC128 24AA256/24LC256/24FC256 24AA512/24LC512/24FC512 I 2 C Serial EEPROM Family Data Sheet Features: 128-bit through 512 Kbit devices Single supply with operation down to 1.7V for 24AAXX devices Low-power CMOS technology: - 1 ma active current, typical - 1 μa standby current, typical (I-temp) 2-wire serial interface bus, I 2 C compatible Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce khz (1.7V) and 400 khz ( 2.5V) compatibility 1 MHz for 24FCXX products Self-timed write cycle (including auto-erase) Page write buffer Hardware write-protect available on most devices Factory programming (QTP) available ESD protection > 4,000V 1 million erase/write cycles Data retention > 200 years 8-lead PDIP, SOIC, TSSOP and MSOP packages 5-lead SOT-23 package (most 1-16 Kbit devices) 8-lead 2x3mm and 5x6mm DFN packages available Pb-free and RoHS compliant Available for extended temperature ranges: - Industrial (I): -40 C to +85 C - Automotive (E): -40 C to +125 C Description: The Microchip Technology Inc. 24CXX, 24LCXX, 24AAXX and 24FCXX (24XX*) devices are a family of 128-bit through 512 Kbit Electrically Erased PROMs. The devices are organized in blocks of x8-bit memory with 2-wire serial interfaces. Low-voltage design permits operation down to 1.7V (for 24AAXX devices), with standby and active currents of only 1 μa and 1 ma, respectively. Devices 1 Kbit and larger have page write capability. Parts having functional address lines allow connection of up to 8 devices on the same bus. The 24XX family is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP and MSOP packages. Most 128-bit through 16 Kbit devices are also available in the 5-lead SOT-23 package. DFN packages (2x3mm or 5x6mm) are also available. All packages are Pb-free (Matte Tin) finish. *24XX is used in this document as a generic part number for 24 series devices in this data sheet. 24XX64, for example, represents all voltages of the 64 Kbit device. Package Types (1) A0 A1 A2 PDIP/SOIC VCC WP (3) SCL A0 A1 A2 TSSOP/MSOP (2) 1 8 VCC 2 7 WP (3) 3 6 SCL SCL SOT-23-5 (24XX00) VCC NC SOT-23-5 (all except 24XX00) SCL 1 5 WP VCC A0 A1 A2 DFN 1 8 VCC WP (3) SCL Note 1: Pi A0, A1, A2 and WP are not used by some devices (no internal connectio). See Table 1-1, Device Selection Table, for details. 2: Pi A0 and A1 are no-connects for the 24XX128 and 24XX256 MSOP devices. 3: Pin 7 is not used for 24XX00, 24XX025 and 24C01C.

2 TABLE 1-1: Part Number 128-bit devices DEVICE SELECTION TABLE VCC Range Max. Clock Frequency Page Size Write- Protect Scheme Functional Address Pi Temp. Range 24AA V 400 khz (1) 24LC V 400 khz (1) None None I 24C V 400 khz I, E 1 Kb devices 24AA V 400 khz (2) I 8 bytes Entire Array None 24LC01B V 400 khz I, E 24AA V 400 khz (2) I 16 bytes Entire Array A0, A1, A2 24LC V 400 khz I I Packages (5) P, SN, ST, OT, MC P, SN, ST, MS, OT, MC P, SN, ST, MS, MC 24C01C 4.5V-5.5V 400 khz 16 bytes None A0, A1, A2 I, E P, SN, ST, MC 2 Kb devices 24AA V 400 khz (2) I 8 bytes Entire Array None 24LC02B V 400 khz I, E 24AA V 400 khz (2) I 16 bytes Entire Array A0, A1, A2 24LC V 400 khz I 24AA V 400 khz (2) I 16 bytes None A0, A1, A2 24LC V 400 khz I 24C02C V 400 khz 4 Kb devices 16 bytes Upper Half of Array P, SN, ST, MS, OT, MC P, SN, ST, MS, MC P, SN, ST,MS, MC A0, A1, A2 I, E P, SN, ST, MC 24AA V 400 khz (2) 16 bytes Entire Array None I P, SN, ST, MS, OT, MC 24LC04B V 400 khz I, E 8 Kb devices 24AA V 400 khz (2) I 16 bytes Entire Array None 24LC08B V 400 khz I, E 16 Kb devices 24AA V 400 khz (2) I 16 bytes Entire Array None 24LC16B V 400 khz I, E 32 Kb devices 24AA32A V 400 khz (2) I 32 bytes Entire Array A0, A1, A2 24LC32A V 400 khz I, E 64 Kb devices 24AA V 400 khz (2) 24LC V 400 khz 32 bytes Entire Array A0, A1, A2 I, E 24FC V 1 MHz (3) I Note 1: khz for VCC <4.5V. 2: khz for VCC <2.5V. 3: 400 khz for VCC <2.5V. 4: Pi A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package. I P, SN, ST, MS, OT, MC P, SN, ST, MS, OT, MC P, SN, SM, ST, MS, MC P, SN, SM, ST, MS, MC 5: P = 8-PDIP, SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP, OT = 5 or 6-SOT23, MC = 2x3mm DFN, MS = 8-MSOP, SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.

3 TABLE 1-1: Part Number 128 Kb devices 24AA V 400 khz (2) I A0, A1, 24LC V 400 khz 64 bytes Entire Array A2 (4) I, E 24FC V 1 MHz (3) I 256 Kb devices 24AA V 400 khz (2) I A0, A1, 24LC V 400 khz 64 bytes Entire Array A2 (4) I, E 24FC V 1 MHz (3) I 512 Kb devices 24AA V 400 khz (2) I LC V 400 khz Entire Array A0, A1, A2 I, E bytes 24FC V (3) 1 MHz I Note 1: DEVICE SELECTION TABLE (CONTINUED) VCC Range Max. Clock Frequency khz for VCC <4.5V. 2: khz for VCC <2.5V. 3: 400 khz for VCC <2.5V. Page Size Write- Protect Scheme Functional Address Pi Temp. Range 4: Pi A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package. Packages (5) P, SN, SM, ST, MS, MF, ST14 P, SN, SM, ST, MS, MF, ST14 P, SM, MF, ST14 5: P = 8-PDIP, SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP, OT = 5 or 6-SOT23, MC = 2x3mm DFN, MS = 8-MSOP, SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.

4 2.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings ( ) VCC...6.5V All inputs and outputs w.r.t V to VCC +1.0V Storage temperature C to +150 C Ambient temperature with power applied C to +125 C ESD protection on all pi... 4kV NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditio above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditio for extended periods may affect device reliability. TABLE 2-1: DC CHARACTERISTICS Param. No. DC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40 C to +85 C Automotive (E): VCC = +2.5V to 5.5V TA = -40 C to 125 C Sym. Characteristic Min. Max. Units Conditio D1 A0, A1, A2, SCL, and WP pi: D2 VIH High-level input voltage 0.7 VCC V D3 VIL Low-level input voltage 0.3 VCC 0.2 VCC D4 VHYS Hysteresis of Schmitt Trigger inputs (, SCL pi) V V VCC 2.5V VCC < 2.5V 0.05 VCC V (Note 1) D5 VOL Low-level output voltage 0.40 V IOL = 3.0 VCC = 2.5V D6 ILI Input leakage current ±1 μa VIN = or VCC D7 ILO Output leakage current ±1 μa VOUT = or VCC D8 CIN, COUT Pin capacitance (all inputs/outputs) D9 ICC Read Operating current 400 ICC Write pf VCC = 5.0V (Note 1) TA = 25 C, FCLK = 1 MHz 1 μa ma ma ma 24XX128, 256, 512: VCC = 5.5V, SCL = 400 khz All except 24XX128, 256, 512: VCC = 5.5V, SCL = 400 khz VCC = 5.5V, All except 24XX512 VCC = 5.5V, 24XX512 D10 ICCS Standby current 1 μa TA = -40 C to +85 C SCL = = VCC = 5.5V A0, A1, A2, WP = or VCC Note 1: This parameter is periodically sampled and not % tested. 5 μa TA = -40 C to 125 C SCL = = VCC = 5.5V A0, A1, A2, WP = or VCC 50 μa 24C01C and 24C02C only SCL = = VCC = 5.5V A0, A1, A2, WP = or VCC

5 TABLE 2-2: AC CHARACTERISTICS ALL EXCEPT 24XX00, 24C01C AND 24C02C AC CHARACTERISTICS Param. No. Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40 C to +85 C Automotive (E): VCC = +2.5V to 5.5V TA = -40 C to 125 C Sym. Characteristic Min. Max. Units Conditio 1 FCLK Clock frequency 2 THIGH Clock high time TLOW Clock low time TR and SCL rise time (Note 1) 5 TF and SCL fall time (Note 1) 6 THD:STA Start condition hold time TSU:STA Start condition setup time THD:DAT Data input hold time 0 (Note 2) 9 TSU:DAT Data input setup time TSU:STO Stop condition setup time TSU:WP WP setup time THD:WP WP hold time 4700 Note 1: Not % tested. CB = total capacitance of one bus line in pf. khz 1.7V VCC < 2.5V 24FCXXX 24FCXXX 24FCXXX 1.7V VCC 5.5V 24FCXXX All except 24FCXXX 1.7V VCC 5.5V 24FCXXX 24FCXXX 24FCXXX 1.7V VCC 5.5V 24FCXXX 1.7 V VCC < 2.5V 2.5 V VCC 5.5V 2.5 V VCC 5.5V 24FCXXX 1.7V VCC 5.5V 24FCXXX 1.7V VCC 5.5V 24FCXXX 2: As a tramitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ) of the falling edge of SCL to avoid unintended generation of Start or Stop conditio. 3: This parameter is not tested but eured by characterization. For endurance estimates in a specific application, please coult the Total Endurance Model, which can be obtained from Microchip s web site: 4: 24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.

6 TABLE 2-2: AC CHARACTERISTICS ALL EXCEPT 24XX00, 24C01C AND 24C02C (CONTINUED) AC CHARACTERISTICS Param. No. 13 TAA Output valid from clock (Note 2) 14 TBUF Bus free time: Time the bus must be free before a new tramission can start 15 TOF Output fall time from VIH minimum to VIL maximum CB pf 16 TSP Input filter spike suppression ( and SCL pi) 17 TWC Write cycle time (byte or page) Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40 C to +85 C Automotive (E): VCC = +2.5V to 5.5V TA = -40 C to 125 C Sym. Characteristic Min. Max. Units Conditio CB FCXXX 24FCXXX All except 24FCXXX (Note 1) 24FCXXX (Note 1) 50 All except 24FCXXX (Note 1) 5 ms 18 Endurance 1,000,000 cycles 25 C (Note 3) Note 1: Not % tested. CB = total capacitance of one bus line in pf. 2: As a tramitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ) of the falling edge of SCL to avoid unintended generation of Start or Stop conditio. 3: This parameter is not tested but eured by characterization. For endurance estimates in a specific application, please coult the Total Endurance Model, which can be obtained from Microchip s web site: 4: 24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.

7 TABLE 2-3: AC CHARACTERISTICS 24XX00, 24C01C AND 24C02C All Parameters apply across all recommended operating ranges unless otherwise noted Industrial (I): TA = -40 C to +85 C, VCC = 1.7V to 5.5V Automotive (E): TA = -40 C to +125 C, VCC = 4.5V to 5.5V Parameter Symbol Min. Max. Units Conditio Clock frequency FCLK Clock high time THIGH Clock low time TLOW and SCL rise time (Note 1) TR and SCL fall time TF 300 (Note 1) Start condition hold time THD:STA Start condition setup time TSU:STA Data input hold time THD:DAT 0 (Note 2) Data input setup time TSU:DAT Stop condition setup time TSU:STO Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new tramission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression ( and SCL pi) TAA TBUF TOF CB khz 250 (Note 1), CB pf TSP 50 (Note 1) Write cycle time TWC Endurance 1,000,000 cycles (Note 3) ms 24XX00 24C01C, 24C02C Note 1: Not % tested. CB = total capacitance of one bus line in pf. 2: As a tramitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ) of the falling edge of SCL to avoid unintended generation of Start or Stop conditio. 3: This parameter is not tested but eured by characterization. For endurance estimates in a specific application, please coult the Total Endurance Model which can be obtained at

8 FIGURE 2-1: BUS TIMING DATA 5 2 D4 4 SCL IN OUT WP (protected) (unprotected) 11 12

9 3.0 PIN DESCRIPTIONS The descriptio of the pi are listed in Table 3-1. TABLE 3-1: Pin Name 8-Pin PDIP and SOIC PIN FUNCTION TABLE 8-Pin TSSOP and MSOP 5-Pin SOT-23 24XX00 5-Pin SOT-23 All except 24XX00 14-Pin TSSOP 8-Pin 5x6 DFN and 2x3 DFN Function A0 1 1 (1) 1 1 User configurable Chip Select (3) A1 2 2 (1) 2 2 User configurable Chip Select (3) A User configurable Chip Select (3) Ground Serial Data SCL Serial Clock (NC) 4 3, 4, 5, 10, 11, 12 Not Connected WP 7 (2) 7 (2) Write-Protect Input VCC Power Supply Note 1: Pi 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages. 2: Pin 7 is not used for 24XX00, 24XX025 and 24C01C. 3: Pi A0, A1 and A2 are not used by some devices (no internal connectio). See Table 1-1 for details. 3.1 A0, A1, A2 Chip Address Inputs The A0, A1 and A2 pi are not used by the 24XX01 through 24XX16 devices. The A0, A1 and A2 inputs are used by the 24C01C, 24C02C, 24XX014, 24XX024, 24XX025 and the 24XX32 through 24XX512 for multiple device operatio. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the 24XX128 and 24XX256 in the MSOP package only, pi A0 and A1 are not connected. Up to eight devices (two for the 24XX128 and 24XX256 MSOP package) may be connected to the same bus by using different Chip Select bit combinatio. In most applicatio, the chip address inputs A0, A1 and A2 are hard-wired to logic 0 or logic 1. For applicatio in which these pi are controlled by a microcontroller or other programmable device, the chip address pi must be driven to logic 0 or logic 1 before normal device operation can proceed. 3.3 Serial Clock (SCL) This input is used to synchronize the data trafer to and from the device. 3.4 Write-Protect (WP) This pin must be connected to either or VCC. If tied to, write operatio are enabled. If tied to VCC, write operatio are inhibited but read operatio are not affected. See Table 1-1 for the write-protect scheme of each device. 3.5 Power Supply (VCC) A VCC threshold detect circuit is employed which disables the internal erase/write logic if VCC is below 1.5V at nominal conditio. For the 24C00, 24C01C and 24C02C devices, the erase/write logic is disabled below 3.8V at nominal conditio. 3.2 Serial Data () This is a bidirectional pin used to trafer addresses and data into and out of the device. It is an open drain terminal. Therefore, the bus requires a pull-up resistor to VCC (typical 10 kω for khz, 2 kω for 400kHz and 1MHz). For normal data trafer, is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditio.

10 4.0 FUNCTIONAL DESCRIPTION Each 24XX device supports a bidirectional, 2-wire bus and data tramission protocol. A device that sends data onto the bus is defined as a tramitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditio, while the 24XX works as slave. Both master and slave can operate as tramitter or receiver, but the master device determines which mode is activated. Block Diagram A0*A1*A2* WP* HV Generator I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches* I/O SCL YDEC VCC See Amp. R/W Control * A0, A1, A2, WP and page latches are not used by some devices. See Table 1-1, Device Selection Table, for details.

11 5.0 BUS CHARACTERISTICS The following bus protocol has been defined: Data trafer may be initiated only when the bus is not busy. During data trafer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditio have been defined (Figure 5-1). 5.1 Bus Not Busy (A) Both data and clock lines remain high. 5.2 Start Data Trafer (B) A high-to-low traition of the line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 5.3 Stop Data Trafer (C) A low-to-high traition of the line while the clock (SCL) is high determines a Stop condition. All operatio must be ended with a Stop condition. 5.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data trafer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes traferred between Start and Stop conditio is determined by the master device.