ECE 545 Lecture 17 RAM. George Mason University
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1 ECE 545 Lecture 17 RAM George Mason University
2 Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques [ UG687 (v 14.5) March 20, 2013 ] Sections: RAM HDL Coding Techniques ROM HDL Coding Techniques ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module [ UG695 (v14.1) April 24, 2012 ] 2
3 Memory Types 3
4 Memory Types Memory ROM RAM Memory Single-port Dual-port Memory With asynchronous read With synchronous read 4
5 Memory Types specific to Xilinx FPGAs Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using CORE Generator 5
6 FPGA Distributed RAM 6
7 Location of Distributed RAM Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 7
8 Spartan-6 Multipurpose LUT (MLUT) 16-bit 32-bit SR x 1 RAM 4-input 64 x 1 ROM LUT (logic) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 8
9 Single-port 64 x 1-bit RAM (1 MLUT) 9
10 Dual-port 64 x 1 RAM (2 MLUTs) Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 10
11 Generic Inferred Distributed RAM 11
12 Distributed single-port RAM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 12
13 Distributed single-port RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(to_integer(unsigned(a))); end behavioral; 13
14 Distributed dual-port RAM with asynchronous read library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr; 14
15 Distributed dual-port RAM with asynchronous read architecture syn of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(to_integer(unsigned(a))); dpo <= RAM(to_integer(unsigned(dpra))); end syn; 15
16 FPGA Block RAM 16
17 Location of Block RAMs Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 17
18 Block RAM Interface 18
19 Block RAM Ports 19
20 Block RAM Waveforms NO_CHANGE mode 20
21 Block RAM Waveforms READ_FIRST mode 21
22 Block RAM Waveforms WRITE_FIRST mode 22
23 Generic Inferred BRAM 23
24 Single-port Block RAM with synchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 24
25 Block RAM Waveforms NO_CHANGE mode 25
26 Single-port Block RAM with synchronous read No-Change Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 26
27 Block RAM Waveforms READ_FIRST mode 27
28 Single-port Block RAM with synchronous read Read-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if rising_edge(clk) then if (en = '1') then do <= RAM(to_integer(unsigned(addr))); if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; end if; end if; end if; end process; end behavioral; 28
29 Block RAM Waveforms WRITE_FIRST mode 29
30 Single-port Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 30
31 Simple Dual-port Block RAM with one port used for reading and one port used for writing LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr_rd : in std_logic_vector(r-1 downto 0); addr_wr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 31
32 Simple Dual-port Block RAM with one port used for reading and one port used for writing architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr_wr))) <= di; end if; do <= RAM(to_integer(unsigned(addr_rd))); end if; end if; end process; end behavioral; 32
33 Criteria for Implementing Inferred RAM in BRAMs 33
34 Using CORE Generator 34
35 CORE Generator 35
36 CORE Generator 36
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