Serial Adapter for I 2 C / APFEL and 8 channel DAC ASIC
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1 Serial Adapter for I 2 C / APFEL and 8 channel DAC ASIC GSI Helmholtzzentrum für Schwerionenforschung GmbH Experiment Electronics Department December 5, 2016
2 Outline 1 Motivation 2 3
3 Motivation Currently two different serial interfaces are foreseen to be used inside the barrel: I 2 C for High voltage DACs APFEL serial configuration interface Both interfaces use single ended lines need ground connection Risk of ground loops Both interfaces are not compatible Requires additional cabling inside the magnet. Wish for an adaptor circuit with additional analogue features raised up. Reuse of tested VHDL entities and available Analogue blocks Integration of 10 bit DACs for HV adjustment. Could also be interesting for End cap HV distribution
4 Outline Motivation Global Architecture 1 Motivation 2 Global Architecture 3
5 Global Architecture Motivation Global Architecture Build an adaptor circuit with a common back end and front ends for I 2 C, SPI and APFEL serial configuration interface Internal Bus 2 I C Master SDC SDA MPIO MPIO Serial Adapter Serial Adapter Serial Adapter Serial Adapter I 2 C Slave Bus Master APFEL If. CLK DOut Din SS SCK MOSI MISO SS SCK MOSI MISO SS SCK MOSI MISO SS SCK MOSI MISO MISO MOSI SCK SS LVDS Driver SPI Slave Bus Master DAC DAC DAC DAC SerialAdapter SerialAdapter Block Diagram Analogue Out Level Converter CMOS - LVDS Termination (100 Ohm) SS SCK MOSI MISO differential LVDS line SPI-Master single ended CMOS line e.g. Microcontroller SPI back end connection
6 Motivation Global Architecture On Chip U Ref Raw HV 10M DAC Output 1M 27n APD Driver Output V M Emitter Resistor Voltage 10b R2R DAC 10p High Voltage 100k For temperature compensation of base emitter diode critical for driving OTA phase margin Current Consumption Circuit of HV Adjustment Spice Simulation 10 bit R2R DAC already used in several ASIC projects OTA design taken from HitDetection Same external circuit as on current HV distribution PCB
7 Motivation Global Architecture On Chip U Ref Raw HV 10M DAC Output 1M 161µm x 73µm V µm x 33.8µm 27n 27M APD Driver Output Emitter Resistor Voltage 10b R2R DAC 10p High Voltage 100k For temperature compensation of base emitter diode critical for driving OTA phase margin Current Consumption Circuit of HV Adjustment Spice Simulation 10 bit R2R DAC already used in several ASIC projects OTA design taken from HitDetection Same external circuit as on current HV distribution PCB
8 Outline 1 Motivation 2 3
9 Motivation First Idea: March 2016 Project launch with financing by University of Bonn after September CM meeting in Mainz November 28th: Dead line for tape out Expected delivery in February 2017 Packaging in QFN32 in early spring Prototyping costs: e mm2 Mini ASIC in UMC 180 nm CMOS technology Serial Adapter for I2 C / APFEL and 8 channel DAC ASIC
10 Backup
11 Costs 1 Mini@sic Block Number of Chips Total costs Packaging Cost/chip 30 (min. number) e 3160 e 2500 e (one slice) e 9660 e 2500 e e e 2500 e (full barrel) e e 5000 e 9.89
12 Digital Design Flow code writing formal verification formality vhdl code synthesis design compiler verilog netlist dig. simulation modelsim Standard cell library timing models layout abstracts IO - Library timing models layout abstracts ASIC layout Place and Route Cadence EDI Floorplanning Placement Clock tree synthesis Routing verilog netlist Abstract replacement Cadence IC6 Final verification Calibre formal verification formality
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