Lesson 3: The Control Unit

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Kristian Conley
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1 Exercises Lesson 3: Computer Structure and Organization Graduate in Computer Sciences Graduate in Computer Engineering Academic course:

2 Lesson 3: Page: 2 / Lets be an elemental computer with the following elements: A 16 operations with two multiplexor attached to their inputs. Accumulator register to store temporal values. A 32 registers file with two outputs ports and one input port. PC attached to data / addresses bus. Main memory of 128 Mbytes of capacity ory reading and writing use two clock periods Data / addresses bus is 32 bits length. Execute next instruction: SHL F, 5 c. Design micro instruction format. Control ory 64k. d. Design the micro program for the above execution phase.

3 Lesson 3: Page: 3 / 12 Dir A Sal A Sal B X0, X1 Y0 Mux X Mux Y Dir B entera Talu oria a Dir A a Dir B R.Ins Desp./ DI. C.Fases Bus de datos / direcciones 2. Lest following elemental computer: A 8 operations : +,, arithmetic shift left and right AND, OR, XOR y logical shift right. Accumulator register to store temporal values. A 16 registers file with two outputs ports and one input port. Autoincremented PC. Main memory of 16Mbytes of capacity. Data bus and addresses bus are 32 bits length. All instruction formats are 4 words length.

4 Lesson 3: Page: 4 / 12 Inc Dir A Sal A Sal B X0 Dir B Mux X entera Mux Y Talu Y0 oria Tbdad Bus de datos Tadbd R.Ins Desp./ DI. C.Fases Bus de direcciones a Dir A a Dir B Execute next instruction: XOR F, [E h] c. Design micro instruction format. Control ory 64k. d. Design the micro program for the above execution phase. 3. Lets be the following elemental computer: A 16 operations. Input to Output transfer is one of its operations, as well ass A-B and B-A.

5 Lesson 3: Page: 5 / 12 Accumulator register to store temporal values. A 8 registers files with one input port and one output port. Autoincremented PC Main ory of 128Mbytes of capacity. Data and Addresses buses are 16 bits length. Data bus content can be transferred to Addresses bus and vice versa. Inc Dir. Salida entera Talu oria a Dir Tbdad Tadbd R.Ins Desp./ DI. C.Fases Bus de datos Bus de direcciones Execute next instruction: SUB [B++], A c. Design microinstruction format. Control ory 32k. d. Design the micro program for the above execution phase.

6 Lesson 3: Page: 6 / Lets be the following elemental computer: Two s: one of them is specialized in multiply and divide operations and the another one in addition and subtraction operations. Both s have an accumulator register to store temporal values. A 32 registers file with one input port and one output port.. Autoincremented PC Main ory of 32Mbytes of capacity. Data and Addresses buses are 32 bits length. Data bus content can be transferred to Addresses bus and vice versa. The whole instructions formats are 32 bits length. Inc Dir. Salida mul / div Talu 2 add / sub 2 Talu2 2 oria Tbdad Bus de datos Tadbd a Dir R.Ins Desp./ DI. C.Fases Bus de direcciones

7 Lesson 3: Page: 7 / 12 Execute the following instruction: Div C, D c. Design microinstruction format. Control ory 32k. d. Design the micro program for the above execution phase. 5. Lets be the next elemental computer: A 32 operations with the possibility of input to output transfer. Temporal and Accumulator registers to store temporal values which cannot be used by assembly language. 16 register files with two output ports and one input port. Stack pointer attached to addresses register Main memory: 16 Mbytes of capacity Data bus content can be transferred to Addresses bus and vice versa. Buses are 32 bits length The whole instruction formats are 32 bits length. Execute next instruction: ADD A, B

8 Lesson 3: Page: 8 / 12 Dir A Sal A Sal B X0, X1 Y0 Mux X Mux Y Dir B entera Talu oria Bus de datos / direcciones Tsp Lsp SP Ttmp Ltmp Tmp R.Ins Desp./ DI. C.Fases a Dir A a Dir B 6. Lets be following elemental computer: Two specialized s: one in multiply and dicide operations, addition and subtraction the another one. Temporal and Accumulator register to store temporal values with no assembly access. 32 registers file with one input and output ports. Autoincremented PC.. Stack pointer attached to addresses bus. Main memory of 32Mbytes of capacity Buses are 32 bits length. The whole instruction formats are 32 bits length.

9 Lesson 3: Page: 9 / 12 Data bus content can be transferred to Addresses bus and vice versa. Inc Dir. Salida 1 mul / div Talu Mux X 2 X0 2 add / sub 2 Talu2 2 oria Tbdad Tadbd Bus de datos Tsp Lsp SP Ttmp Ltmp Tmp R.Ins Desp./ DI. Bus de direcciones C.Fases a Dir Execute following isntructions: ADD [[B h]], [C h] 7. Lets be a elemental computer as follows.: Two specialized s. a fixed point and a floating point one.

10 Lesson 3: Page: 10 / 12 Temporal and Accumulator registers to store temporal values which cannot be used by assembly language. Two 32 registers file with one input and output ports. One for fixed point registers and the another for floating point ones. Autoincremented PC Main ory of 4Gbytes of capacity. Buses are 32 bits length. The whole instruction formats are 32 bits length. Data bus content can be transferred to Addresses bus and vice versa. Inc Dir A Salida de coma fija X0 Mux X Mux Y coma fija Y0 Talu Ltmp Tmp Ttmp oria 2 Sal A de coma flotante Sal B Talu2 2 2 coma flotante Mux X X0' Mux Y 2 Y0' Tbdad Tadbd a Dir A Bus de datos Bus de direcciones R.Ins Desp./ DI. C.Fases Dir A Dir B a Dir B Execute following instruction: MULF D, C, 3.27

11 Lesson 3: Page: 11 / Lets be next elemental computer: A 16 operations. 3 registers file: B, C and D. Main ory of 640Kbytes. Data and Addresses buses are 32 bits length Execute following instruction: SUB B, [ C h ] a. Modify bellow computer if needed b. Describe elemental operation to perform in each execution phase c. Draw above instruction chronogram

12 Lesson 3: Page: 12 / Lets be following elemental computer: A 16 operations. Datapath contains PC, SP and Accumulator register, as well as a 3 registers file. Main memory 32 Kbytes of capacity. Data bus: 8 bits. Addreses bus: 16 bits. Instructions have different sizes Execute next instruction: POP B

Lesson 2. Instruction set design

Lesson 2. Instruction set design Exercises Lesson 2. Computer Structure and Organization Graduate in Computer Sciences Graduate in Computer Engineering Lesson 2: Page: 2 / 6 1. Lets a 32 bits word computer with a register file of 16 registers