Improve Reliability With Accurate Voltage-Aware DRC. Matthew Hogan, Mentor Graphics

Transcription

1 Improve Reliability With Accurate Voltage-Aware DRC Matthew Hogan, Mentor Graphics

2 BACKGROUND Consumer expectations for longer device operations at sustained performance levels means designing for reliability is no longer an optional product feature, but a necessary and integral part of a product s specifications. Power challenges in today's integrated circuit (IC) designs create a significant increase in verification complexity. Critical design rule checking (DRC) of variable spacing rules for densely packed multi-voltage nets is often verified with the traditional use of marker layers, a tedious, time-consuming, and error-prone technique. Without an efficient means of verifying variable spacing within nets, designers often play it safe and simply apply maximum spacing throughout specific areas of a design, wasting valuable design area. Or worse, by the inadvertent omission of these marker layers, they use process manufacturing rules that place these nets too close together for the design requirements. Designers need verification tools and techniques that go beyond the traditional triumvirate of DRC, LVS, and ERC to provide robust reliability verification throughout the design flow and ensure maximum design efficiency. With mixed signal, memory, and logic elements sharing the same die, it is common to have multiple voltages, with the voltage for a specific region selected for the best functional operation. In addition, each voltage may be associated with multiple power domains discrete portions of the design that can be turned on and off. Depending on how nets traverse within a design, signals of different voltages may be near each other. This difference in voltage values can create electrical fields that can influence sensitive areas on the chip and lead to reliability issues, particularly for automotive and other high power applications [1]. To protect these nets from time-dependent dielectric breakdown (TDDB), which can be caused by having nets too close to each other for their respective voltages, additional spacing rules are developed that specify power domain spacing based on the voltage delta. In general, as the change in voltage increases, so does the spacing that is required between the two domains. With designs today often containing tens, or even hundreds, of power domains, these spacing rules can explode in intricacy (Figure 1). Figure 1: In a multiple-voltage design, different spacing checks are required, based on the voltage change between the two areas being analyzed. The spacing between each block combination depends on the difference in voltage between the two blocks. (Image source: bwrc.eecs.berkeley.edu/cic/die_ photos/pentium.gif) Traditional DRC spacing rules consider only the physical manufacturing aspects of an integrated circuit (IC) design. Traditional electrical checks use a single device/pin-to-net relation. In contrast, reliability requirements can often only be described by a topological view that combines both circuit description and physical devices [2]. The rules defining the spacing checks that must be performed when a high-voltage net is routed close to a lowvoltage net are often quite complex, and require analysis of both the physical layout and the circuitry. In older design flows, designers managed these types of checks by manually adding marker (CAD) layers to trigger additional DRC checks in these areas, or to identify these portions of the design for visual inspection. Marker layers require a designer to manually determine how voltages propagate throughout a design, then manually mark the 2 [5]

3 correct regions where variant spacing is required. Not only are marker layers time-consuming to create, but it is often exceedingly difficult to maintain them with any accuracy as design changes occur [3]. Alternatively, without a simple and efficient way to analyze voltage changes in relation to physical spacing, designers simply applied maximum spacing rules throughout that portion of the design, creating larger designs than necessary for the sake of meeting tapeout schedules. Both of these techniques were a best effort, error-prone solution for established process nodes, but as we move toward more complex multiple-voltage designs, while simultaneously looking for more design real estate, designers need to be able to identify these voltage changes quickly and easily, accurately apply the appropriate spacing rule to each occurrence. Another critical concern is the interactions of the different power states at the transistor level, where verifying bulk connections, floating wells, and other physical implementation details is critical to avoiding latch-up conditions and ensuring high reliability. Until now, SPICE simulations have been used in an attempt to cover all the possible scenarios. Unfortunately, these simulations require exhaustive test vectors to exercise all combinations. This requires detailed waveform analysis to decipher design errors, some of which contain subtle changes that may be easily overlooked. Finding these subtle design errors using traditional SPICE methods is often tedious and error-prone, and almost always time-consuming. In addition, mastering the use of these tools and the interpretation of their results requires significant experience in the application space and detailed familiarity with the design being evaluated. AN EFFICIENT AND EFFECTIVE SOLUTION WITH CALIBRE PERC Comprehensive and practical reliability verification coverage requires an approach that does not rely on manual marker layers, visual inspection of layouts, or time-consuming simulations. Calibre PERC is a powerful reliability verification platform that provides designers with a diverse range of advanced verification capabilities. Not just another point tool, Calibre PERC provides a full-featured reliability verification solution that supports designers throughout the design and sign-off process with a variety of capabilities and techniques. Calibre PERC s ability to use both netlist and layout (GDS) information simultaneously to perform rule checks that incorporate both layout-related parameters and circuit-dependent values enables designers to address the complex spacing verification requirements both quickly and accurately. Device and nets connectivity is established for the design. Typically this netlist is extracted from the layout. Using its built-in voltage propagation capability, Calibre PERC traces voltages throughout a design, without the use of SPICE simulations or manual markers, then identifies nets and devices subject to voltage-aware DRC constraints. Once the voltages are known, designers use these values to run DRC net spacing checks that are dependent on the voltage difference between different nets [4] [5]. If desired, the entire flow can be run from a single Calibre PERC invocation. These checks not only enable robust protection against TDDB, but also enable design teams to save significant design space by applying only the spacing required for each voltage combination. By using its voltage propagation capability in conjunction with its knowledge of the nets, devices, and the location of each of these in the design, Calibre PERC helps designers ensure the right DRC checks are run for all of the voltages in the design, and that design area is conserved through the use of minimum spacing. Figure 2 illustrates a high-level view of the voltage-aware DRC flow [5]. 3 [5]

4 Calibre PERC rule decks may also be easily augmented to include custom verification requirements that extend beyond or expand upon standard foundry rule decks. Users can insert custom reliability verification into their existing design flows as part of an integrated Calibre platform for cell, block, and full-chip verification. Combining rules expressed in the proprietary SVRF and the Tcl-based TVF language across all applications provides users with flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries. As always, debugging is a key component of any verification flow. Calibre PERC provides an integrated debugging solution that provides extensive coverage and is easy to use. Deterministic checking helps eliminate even the most subtle reliability errors quickly and efficiently, compared to the use of manual marker layers and visual inspection (Table 1). Figure 2: Voltage-aware DRC layout checking flow with Calibre PERC [5]. TABLE 1. Comparison of Calibre PERC to Marker Layers and Visual Inspection Items Calibre PERC Marker Layers Visual Inspection Rules Coverage over 90% under 30% under 10% False Error 0 to very low, waiver many, waiver always Tool Integration Topology, LVS, DRC, P2P, CD DRC+manual marker manual examination Tool Quality sign-off level dependence no quality Programmable fully partial never Run Time minutes~hours minutes~hours hours~days Human Error never sometimes always User Usage automated semi-automated manual Calibre PERC readily integrates into your design flow, while Calibre RVE provides a results viewing and debugging environment that highlights results and geometries, and accesses connectivity information, to make debugging reliability checks easy, quick, and thorough (Figure 3). 4 [5]

5 Figure 3: Calibre PERC results can be easily and efficiently reviewed and debugged in Calibre RVE. Accurate and repeatable reliability verification is now a critical capability, both for advanced node designs and the increasingly complex products being produced at established nodes. Voltage-aware DRC is an essential component in the reliability assessment of a design. Calibre PERC is the only comprehensive solution capable of verifying both the geometrical and electrical constraints in a single platform that is needed to ensure that nets are protected and that design spacing is maximally utilized. As part of the Calibre platform, it integrates easily into existing signoff flows, with comprehensive debugging provided by Calibre RVE. Calibre PERC provides an easy-to-use, automated, and customizable verification solution that can ultimately reduce both cost and time to market, while providing the diagnostic insights today s designers need to improve yield and device reliability. To learn more about Calibre PERC s full range of capabilities, visit our website at: 5 [5]

6 REFERENCES [1] Medhat, D. Circuit reliability challenges for the automotive industry, EE Times EDA Design Line (Jan 2013). URL: [2] Kollu, K., Jackson, T., Kharas, F., Adke, A., Unifying Design Data During Verification: Implementing Logic-Driven Layout Analysis and Debug, IC Design & Technology (ICICDT), 2012 IEEE International Conference on, pp.1,5, May June doi: /ICICDT URL: [3] Robertson, C., Circuit Reliability: Old Problem? New Problem? Or Both?, EE Times EDA DesignLine (June 2013). URL: [4] Lescot, J., Bligny, V., Medhat, D., Static Low Power Verification at Transistor Level for SoC Design, Proc. ACM/ IEEE International Symposium on Low Power Electronics and Design (2012), Doi: / [5] Hogan, M., Srinivasan, S., Medhat, D., Lu, Z., Hofmann, M., Using Static Voltage Analysis and Voltage-Aware DRC to Identify EOS and Oxide Breakdown Reliability Issues, IEEE Electrical Overstress/Electrostatic Discharge Symposium (2013) For the latest product information, call us or visit: w w w. m e n t o r. c o m 2013 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners. MGC TECH11360