Harmony-AMS Analog/Mixed-Signal Simulator

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Bernice Daniel
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1 Harmony-AMS Analog/Mixed-Signal Simulator Yokohama, June 2004 Workshop 7/15/04

2 Challenges for a True Single-Kernel A/MS Simulator Accurate partition of analog and digital circuit blocks Simple communication definition between analog and digital blocks Correct initialization of analog and digital simulators Synchronization between two simulators during run-time Convergence Single viewer that simultaneously displays any combination of digital and analog signals Industry-proven and accepted analog and digital simulator from a single vendor Lack of an AMS language standard that is complete, commonly agreed upon and widely accepted - 2 -

3 Harmony-AMS Analog/Mixed-Signal Simulator with Integrated AMS Viewer - 3 -

4 Harmony-AMS Overview Harmony-AMS is a mixed-signal design and verification solution based on analog simulator SmartSpice and the veteran Verilog (IEEE ) simulator Silos. Harmony-AMS provides a comprehensive environment that enables design and verification of full-chip mixed-signal designs with built-in support for Verilog-AMS language defined by the Accellera 2.1 standard. It provides a combination of accuracy, performance and capacity with the flexibility of simulating design abstractions in any combination of Verilog, SPICE, Verilog-A and Verilog-AMS Harmony-AMS provides a platform for the transfer of analog designs from Gateway Schematic Editor, a complete graphical analog design environment supporting design creation and exploration including optimization. Post layout analysis and verification, using back-annotation of parasitic data, for DRC/LVS correct layout is accomplished using SPRINT Transistor Level Simulator - 4 -

5 Harmony-AMS Single Waveform Viewer Data Tips in the Source Window display value, scope, and time of the highlighted expression at the T1 marker in the Data Analyzer

6 Harmony-AMS and SmartView for Complex Plots Harmony-AMS can save vectors within any hierarchical subcircuit for SmartView graphical analysis including annotated eye diagram, constellation, FFT analysis, and vector calculator - 6 -

7 Interactive Debugging Environment Interactive, interpreted Verilog-AMS environment provides a set of multi-tasking utilities to edit HDL source, set incremental breakpoints, stepping or timed simulation, real-time viewing, and error detection Multi-window customizable Data Analyzer controls pan and zoom, timing markers, using interactive drag & drop capture, and display for signals and expressions for analog and digital waveforms Trace Mode graphically traces all fan-in connections to any signal through all levels of circuit hierarchy instantly Watch window displays or forces state values of specified signals and variables while single-stepping all set up through drag & drop for designer convenience Interactive Source Code Editor displays line numbers for stop, start, and breakpoints, Data Tips to view the values of analog and digital variables and expressions, and Verilog code coverage information - 7 -

8 Communication System using DPLL for System Clock Recovery - 8 -

9 Digital Phase Lock Loop for System Clock Recovery Analog (SPICE + Verilog-A) Digital (Verilog-D) - 9 -

10 DPLL First pass of the DPLL is all in Verilog-AMS All modules are represented in behavioral form

11 XOR - PD LPF_in D_clock VDD VDD/2 p/2 p

12 Low Pass Filter (LPF) LPF_out LPF_in

13 VCO

14 Divide By N Circuit

15 PLL

16 TestBench

17 Harmony-AMS Single Window Environment

18 DPLL Second pass of the DPLL is all in Verilog-AMS except VCO is now a SPICE netlist

19 VCO

20 VCO -Subcircuit

21 VCO Netlist

22 Harmony-AMS Single Window Environment

23 Harmony-AMS Single Kernel Simulator Third pass of the DPLL is an architectural change with a Verilog-D Phase Frequency Detector and a analog netlist for a charge pump

24 Harmony-AMS Single Kernel Simulator

25 Harmony-AMS Single Window Environment

26 Harmony-AMS Single Kernel Simulator DEMONSTRATION

27 Summary Single-kernel engine provides optimal co-simulation initialization, synchronization, convergence, and accuracy Single parser reads Verilog, SPICE, Verilog-A and Verilog-AMS input decks and testbench descriptions to automatically partition design at correct level Single window viewing and plotting for both analog and digital waveforms Compliant with Accellera 2.1 standard for Verilog-AMS and Verilog- A, IEEE standard for Verilog-D and Programming Language Interface (PLI), and HSPICE netlist/command Provides the most accurate circuit simulation results and robust convergence for critical mixed-signal designs Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor Efficient use of CPU resources optimizes run-time performance

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