Implement Imaginations. VisualSim Training. Mirabilis Design Training

Transcription

1 Implement Imaginations VisualSim Training

2 A Overview on Mirabilis & VisualSim Corporate Headquarters 1159 Sonora Ct, Suite 116 Sunnyvale, CA USA Tel : Fax: online_support@mirabilisdesign.com

3 Mirabilis Design Provider of Systems Engineering applications and services Founded in 2005 Offices in Sunnyvale, CA, USA and Southern California Delivery infused by a distinct culture of customer satisfaction Over 55+ customers and 100 licenses Comprehensive System Design Software Provider

4 Introduction to Conceptual Design Is this the Right Design? Translation from product concept to implementation is critical link Traditional methods are ad-hoc VisualSim approach reduces risk s and speed s design Concept System Architecture Behavior Mapping Architecture refinement VisualSim Way Old Way HDL, Software & Schematics Field Testing HDL, Software & Schematics Field Testing Errors in early stage cannot be rectified with optimized manufacturing

5 Purpose of System Modeling Select the right platform Processor, FPGA or SoC Hardware-Software partitioning Trade-off power, performance and functionality Develop full system prototype Visibility into complete system operations View both implementation agnostic and effects When to perform system simulation Identify capacity limitation and bottlenecks Performance, Power or Functionality is non-deterministic

6 VisualSim Capabilities Traffic Analysis Flow control and arbitration algorithms System sizing Micro Architecture modeling Software design and trade-off

7 Concept To Specification Need to design a new phone -Must play MP3 files -Java games so, accelerator -Need a up, DSP and FPGA Idea Discussion Customer Requirements Build Optimize Validate Performance Analysis Resource Sharing Task Partitioning Requirements Checking Specification Architecture Component/Device Selection Functional Partitioning Parameters/Attributes Interfaces and Pin Definitions Frame/Packet Fields

8 About Modeling Library Setup and Test Infrastructure Traffic Generators and stimulus Over 2000 Results, Statistics, Plotter and Viewers Performance and Resource modeling Implementation-accurate hardware/software components Embedded power modeling at software and hardware level Extensive Model Templates Framework for 40+ applications with an example Examples provided to explain and use library component Over 400 building blocks and 600 RegEx functions to provide total solution 2/8/2017

9 Other VisualSim Features Infrastructure Library Manager Dynamic Instantiation Methodology Modeling, simulation and analysis environment Graphical and hierarchical modeling Mixed abstractions & mixed-signal modeling Application-Specific Signal, audio, video and image processing, analog, controls Wired Networking and Wireless Sensor Networks Modeling libraries, mixed abstraction and hierarchical development 2/8/2017

10 Fundamentals of Using VisualSim

11 VisualSim Organization Modeling GUI available in VisualSim are: Block Diagram Editor Expression Evaluator Text Editor Simulation - Graphical Simulation and Batch Simulation Post Processor In addition to the blocks in Result library Post Processor can be used to checkout the result Documentation Every block contains documentation Demonstration Systems Several demo models are available as examples 2

12 Parts of the Block Diagram 1. Menu-Bar 2. Toolbar 4. Annotations 6. Variables 5. Parameters 7. Setup 10. Architecture 3. Libraries 12. Mapping 11. Use cases Behavior 8. Traffic 9. Report 3

13 FSM GUI States Ports Transitions (CTRL+Drag) Guard Condition Set Action Note: Actions in State and Transitions of a FSM-Hierarchical are defined as Block Diagrams, Custom-Code or other State Machines 4

14 Block Diagram Details Configure Ports Types of Ports Input Port Output Port Block Context Menu Relation Relations and Connections 5

15 Understanding Port Types Data types are polymorphic identified at the ports Ports can be specified as: int, double, long, float, boolean, string, arrays or data structure Note: Port types on either side of link must match Ports can also be unspecified: general or unknown Simulator dynamically adapts to the connected ports, if both sides are unspecified User-added ports must always be set to a minimum of General Port types of library blocks If a port type is fixed such as int, string or double, this cannot be modified and the port connected to it must be modified Exceptional Cases: Only unknown and general can be modified 6

16 Parameters Definition Usage Types Constant, start-up configuration attribute Used to simulate scenarios Any block in the BDE can access these values Export block parameters to link to the BDE parameters Vary Parameter dynamically during simulation - usage is restricted Generic parameters - Scalar and String Expression Parameter File Parameter Shared Parameter 7

17 Introduction to Libraries

18 Library Folders View the Block Documentation Link from VisualSim Front Page

19 Block Color Coding Switches, Math and Basic Queues Data Structure and RegEx Virtual Connections Display and Plotting Resource Hierarchical INIT, RegEx, Const

20 Traffic, Reports and Interfaces Traffic Sequence, distribution-based, files and clocks Plotters and Debugging Tools Real-time viewers, animation and breakpoint Text, export, statistics Pre-configured Analysis Power- Instantaneous, average and discharge Performance- Latency, buffer, hit-ratio, stall-times, utilization, throughput, I/Os second Interfaces C/C++/Java, Python, MatLab, Excel, XML File I/O, serial I/O, device I/O, CORBA and RMI, Database SystemC, HDL, STK No Post Processing Required- Development to Analysis together

21 Modeling Libraries Performance Resource Channels, pipeline, SystemResource (schedulers), queues, active and quantity resources Cycle-Accurate Architecture Generators Processor (up, DSP and Custom), memory, cache Profile-based software sequence generator Linear, switched and Req-Ack bus Pipeline, DMA, Controllers Bridges, Switches (Blocking & non-blocking) Behavior Block-based, C-like scripting, Java/C/C++, SystemC Application-Specific Signal and image processing, analog, controls Wired Networking and Wireless Sensor Networks No Programming Required- Accelerate model development

22 Standard Technology Traffic SoC Board-Level Processors Distribution and Sequence Trace file input Instruction profiler Reports (2000) Latency, Throughput, Utilization Ave and peak power Custom generator AMBA (AHB/ APB/ AXI) CoreConnect- PLB & OPB NoC, Virtual Channel Memory Controller SDR, DDR, DDR2, DDR3 QDR, RDRAM LPDDR, LPDDR2 VME- Parallel & Daisy PCI/PCI-X/PCI-Express SPI 3.0 Rapid IO 1553B FlexRay CAN, CAN-FD ARM PowerPC- Freescale and IBM Intel and AMD TI MIPS Tensilica Renesas SH Resources Time & quantity resources Assignment language Custom development script 600 RegEx functions Storage Flash Disk Memory Controller (Fixed, Round-Robin, Priority) Multi-Port Multi-Channel Controller Networking Switched Ethernet Resilient Packet Ring RP3 Wireless LAN Bluetooth Spacewire FibreChannel FireWire TTEthernet Xilinx FPGA Hard & Soft IP Virtex Spartan Processors, Memory, Bus DMA, FSL, APU and MPMC-2

23 Power Modeling Used in concept stage and refined during design stage Based on dynamic activity using data sheet information Reports Peak, instant and average power Generate power profile for verification Methodology Spreadsheet of the power level/state for each device Combines effects of transitions and controller speed RegEx Functions Early Power estimation enables high quality specification

24 Modeling for Accuracy Abstraction Level Blocks Scripts Coding Type of Library Generic Specific n/a n/a Example Accuracy Limited by Queuing Scheduling AXI, DDR3, Processor ~85% User s Hardware/ Software 95%~ C/C++/RTL /SystemC Details level entered into model 95%~ Details level None (can be exactly to the hardware)

25 Selecting the right block- 1 Traffic, Test Bench, Clock Traffic>Clock Traffic>Traffic Analysis, Reports, Display Results->TimeDataPlotter Results->Statistics Result->TextDisplay Math and Logical Use RegEx language Write/Read File Import Traffic Reader File Reader File Writer Excel XML C Code Application SystemC Verilog

26 Selecting the right block- 2 Event Resources Queues Event Queue Timed Resources Behavior Algorithm- Script Existing algorithm- C, Java One Queue to One Server- Timed Q Symmetrical: Server_N_Resource Combine multiple parallel resources- Server (a.k.a Smart_Timed_Resource) Distributed requests- SystemResources Quantity Quantity_Based Channel Used to define logic for each Server Lookup Sequence- Processing Sequence with routing- Decision Arrays or Database Temporary storage If content is not important, then use Queue If content determines activity, use arrays 1-to-many or 1-to-1 channels 10

27 Selecting the right block- 3 Hardware RTOS Standard blocks Server: SLOT type Queues + Script for custom scheduling (Queues block is also known as Smart_Resource) 11

28 Realize Imaginations VisualSim Tools, Licensing and Usage

29 Tool Organization VisualSim Architect Library such as Hardware Architecture, Resources, Script etc. Interfaces such as Verilog, SystemC, Application etc. Utilities such as PowerTable Technologies such as DDR3, Cache and PCIe VisualSim Post-Processor VisualSim Explorer VisualSim Batch Simulation

30 VisualSim Architect Used for Model Construction, analysis and verification Users: Usage: Model developers of core components such Interconnects, Processors and Multimedia Architects assembling systems Firmware designers Import code from pre-built models Construct models using the pre-built library or combine multiple blocks to create new libraries 3

31 Batch Simulation and Post Processor System analysis using pre-existing models Users: Usage: Chip architects Performance analysts RTL developers Batch simulation using existing models by varying parameters View results from batch simulation using Post Processor 4

32 VisualSim Explorer Trade studies, documentation, reference designs, explore variations of the specification Users Usage Marketing, Management, Customers (reference design) Create BoM (customization required) Casual users such as FAE and implementation teams Training on Wiki Conduct complex analysis using pre-built models in a familiar graphical environment. Provide customers early view on a new device or system Remote access via the Web but no access to tool install Conduct offsite or customer demonstration with latest models Use for sharing early specification with design teams, customers and partners from within documentation 5

33 Advantages of VisualSim Explorer Zero learning curve Does not consume Architect license and reduces cost No cost for external and other teams to access models and results. Anyone anywhere can conduct analysis, restrict visibility to details IP is not distributed to people or organization that have no need for them 6

34 Introduction to Modeling

35 Architectural Concept to Executable Specification Question answered by the Model What is Cache Utilization and Latency? Incorporating the Flow, Scalability and Reusability Level of Abstraction, Speed vs. Accuracy Incorporating System-level settings Data Structures, Parameters and Variables 2

36 Concept to Specification Top Down Modeling Process Conceptualize -> Thinking -> Question, Abstraction Conceptualize -> Thinking -> DS, PARAM, VAR Conceptualize -> Thinking -> Blocks, Output Wait some time and Repeat Bottom Up Modeling Process Conceptualize -> Thinking -> Blocks, Output Conceptualize -> Thinking -> DS, PARAM, VAR Conceptualize -> Thinking -> Question, Abstraction Wait some time and Repeat Best is a combination of both 3

37 System Definition Methodology Separation of Workload, Behavior, Architecture and Analysis Data Structures carry information (Fields) through model Manipulate Data Structure Fields to define algorithm Variables to communicate between blocks and DS Virtual Connections simplify data flow through the model 4

38 Abstraction Sub-system under study Resource utilization, system latency or both? Sub-system is defined in detail while abstracting rest of the system Environment can be treated as traffic generators or sinks Select required modeling abstraction Performance/ queuing: Limited relevance to underlying circuits and software Behavior/ functional: Functions to manipulate incoming data Architecture/ transaction: Add implementation constraints to performance model Software-driven: C/C++/Java Implementation (RTL, Circuit and transistors): EDA Vendor 5

39 Constructing a Performance Model Break down model into elements Traffic sources - Agreeing on traffic profiles Defining behavior or actions performed in the system Constructing the data flow and the control flow Connectivity of hardware and software architectures Mapping the behavior tasks to the architecture Analysis expected Determine regions for analysis Types of results - latency, throughput, utilization etc. 6

40 Design Methodologies Data-flow driven Statistical modeling of application with minimal implementation restriction Sub-system design evaluating hardware topologies Separation of Behavior and Architecture Hardware-Software partitioning Software code optimization Optimize task or application for latency and power 2/8/2017

41 Methodology Flow-Diagram Algorithm & Protocol Development Flow-chart of Application (s) Mapping Repeat to Optimize Annotate Flow Chart with delays and contention (or) Define Architecture Simulate & Analysis Generate Specification Verification & Software optimization 2/8/2017

42 Separation of Behavior and Architecture Four Parts Model Construction and Setup Experimentation Model Refinement Generate Specification Return for verification and software code optimization 2/8/2017

43 Separation Methodology: Model Construction Setup Input Flowchart Mapping Platform Algorithm - MatLab Protocol - VisualSim Model Functional flowchart- One per Application Assign Flowchart tasks to cores and IP Model hardware platform with Cores and IP Define Attributes 2/8/2017

44 Separation Methodology: Simulate and Analysis Good but has hot-sports Go To Refinement Simulate Plots & Statistics Meet Requirements Need more study Change Parameters & Simulate Vary mapping, timing, size and power attributes Far-away Restart with Model Setup 2/8/2017

45 Separation Methodology: Refinement Refine Algorithm Modify Flow Attribute Change Experiment Software or parallel flow Define data and interfaces Vary mapping, timing, size and power attributes Repeat Simulate & Analysis Hardware IP Move to Platform

46 Separation Methodology: Software Optimization and Verification Detailed Refinement Experiment Experiment Vendor ISS VisualSim Fast Functional model Repeat Simulate & Analysis Compare with System Model Vcd file or RTL

47 Software Code Optimization Code QEMU Instruction & Device access trace System Model in VisualSim (File I/F) (CORBA I/F) Run Iterations by varying system attributes & traces Execute Trace on Model View Power and Performance Metrics

48 Trace from Instrumentation Application Processor Instruction count and cycles Instruction and Data cache- Read/Write Memory Access Peripherals Access by word lines for each device using memory map information Note SDK contains no timing information

49 Trace Sample {InstructionCount = 11299, InstructionCycle = 57455, ICacheHit = 4730, ICacheMiss = 952, DCacheReadHit = 4012, DCacheReadMiss = 383, DCacheWriteHit = 2752, DCacheWriteMiss = 65, DDR_Read = 1335, DDR_Write = 448, SimHostTime = , SimTargetTime = 57456, Index = 0, ioreadcount={4, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34}, iowritecount={2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 2, 9}, processorid=0}

50 VisualSim Platform Screen Shot

51 Standard Profiles Performance Power Response time per application or method Utilization of system resources to identify system bottleneck Cache/memory utilization Power consumed per application or method Battery discharge Device power profile

52 VisualSim Profile Output Application Performance Hardware Performance Power Profile