Cadence SystemC Design and Verification. NMI FPGA Network Meeting Jan 21, 2015
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1 Cadence SystemC Design and Verification NMI FPGA Network Meeting Jan 21, 2015
2 The High Level Synthesis Opportunity Raising Abstraction Improves Design & Verification Optimizes Power, Area and Timing for Front End & Back End Tools Moves Verification and Debug up to where it is more efficient Greatly Improves Design Reuse/Retargeting HLS is Proven on Wide Variety of Cutting-Edge Designs Hand-RTL Quality for: Datapath, Control and Mixed Designs Common for designs over 30M gates and >1GHz HLS Provides Significant Competitive Advantages Leading Semiconductor Companies are Changing their Design Methodologies for Productivity and Performance Reduces Costs and Provides Fastest Path to Verified Silicon Cadence Design Systems, Inc..
3 What is High Level Synthesis (HLS) High Abstraction SystemC describes functionality without micro-arch or implementation details This SystemC is always golden, and is the primary functional verification target Less code to write/debug/maintain HLS is used to explore various implementations Explore and trade-off area, timing, power, pipelining, clocks, tech nodes, etc. Outputs functionally equivalent RTL (or gates) plus simulation models/wrappers Fits into existing flows RTL What SystemC TLM Cadence HLS RTL Compiler Or FPGA synthesis Scripts, Wrappers How High-Level Constraints Performance Area/Power Tech Lib Cadence Design Systems, Inc..
4 Cadence HLS targeting FPGA Design constraints SystemC C-to-Silicon Compiler API to Altera/Xilinx logic synth RTL FPGA synthesis XST/POF Area/Timing Estimates Integrated with Xilinx/Altera logic synthesis tools (since 2008) Supports all end devices Provides accurate timing/area estimates Flexible scheduling to meet QoR needs Utilization vs max clock speed Supports DSP48 blocks Outputs standard RTL to be synthesized by Quartus/Vivado Cadence Design Systems, Inc..
5 How does HLS improve productivity Untimed SystemC is more abstract than RTL This eliminates: Breaking down logic into clock cycles Manual creation of the FSM Explicit memory management Explicit register management And more. HLS automates all low-level RTL requirements "We don't want our engineers writing Verilog, we want them inventing concepts and transferring them into silicon and software using automated processes. Yoshihito Kondo GM, Sony Corporation in EDA Graffiti, July 2009 Functionality Architecture Constraints Schedule of operations FSM encoding Area reduction Timing Clock gating Pipeline balance Consistent RTL style Sharing components User Manages HLS Automatically Manages Cadence Design Systems, Inc..
6 Parallel Design and Verification RTL flow RTL design RTL coding * time to completion RTL verification With RTL flows, the verification cannot start until the design is ready, many months after the start of the project HLS flow * SystemC design SystemC verification RTL verification productivity improvement With HLS verification can start at the same time as the design time to completion * = time of first test vectors running time SystemC model stays golden HLS ensures its always in sync with RTL Parallel design and verification yields large productivity improvement! Cadence Design Systems, Inc..
7 High-level synthesis is not same as software... Algorithm may be the same, but the implementation has different needs Interface specification and verification Data organization, flow, and storage Software models do not have enough information for aggressive HW Software can assume infinite storage with equal (fast) access time, but Hardware must trade off storage size vs. access time SystemC required if QoR and predictable RTL closure is important Similar RTL-style block partitioning, but leverages higher abstraction Cadence Design Systems, Inc..
8 SystemC enables System Design ANSI C provides syntax for Computation Functions and arithmetic expressions Verify the math fast with no timing Great for pure algorithms C++ adds Object-Orientation Classes, objects, and templates Great for managing complexity SystemC adds System-Level constructs Structure: hierarchy, modules and ports Concurrency: processes Communication protocols: transaction-level queues, signals, events and waits Precision: fixed-point & bit accurate data types Great for hardware design and verification SystemC system-level C++ ANSI C functionlevel High Level Synthesis Cadence Design Systems, Inc..
9 Cadence synthesizable SystemC IP Pre-verified building blocks accelerate design and verification Interface IP Generator Memory IP Generator CellMath Floating-Point IP Category Data types Building blocks Generic communication Configurable bus interfaces Custom interfaces Available IP Blocks Fixed point Complex Floating point Computational math FIFOs Line buffers CDCs Memories Point-to-point channels with put()/get() APIs Simple bus AXI3 AXI4-Lite, AXI4 Can be created by users Design services available Cadence Design Systems, Inc..
10 High-level verification With SystemC Verify algorithms, interfaces, synchronization IP Blocks Design Blocks AXI 4 Synchronization Channel Configuration Register AXI Slave Interface Decoder and Registers C D C Error Diffusion 32-bit Unpack Filter Zoom pix-24 pix-3 Pack 32-bit Line Buffer 24-bit pixels 5x5 Line Buffer 24-bit pixels 2x2 IMG Accelerator Dual Port Adapter Feedback RAM Cadence Design Systems, Inc..
11 High-level synthesis applications Control Mixed Datapath DSP IP Graphics processing Video processing Image processing Wireless signal processing Security Error correction Automotive Wireless infrastructure Ethernet Microcontroller Memory I/F control Printer control Cache controller DVD/CD Controller Cadence Design Systems, Inc..
12 Cadence High-Level Synthesis Interface IP Generator SystemC IDE Memory IP Generator Floating Point IP Technology Library Directives Synthesizable Behavioral Models IP Datapath Control Flow Automation & Integration Cadence HLS RTL Compiler Inside Results Visualization Power Performance Area Optimized RTL Combined strengths of Cynthesizer and CtoS Worlds most proven HLS technology Cadence Design Systems, Inc..
13 (mw) Summary: Why use high-level synthesis? SystemC RTL in 10 days vs. manual RTL in 3 months FPGA retargeting in 1-2 days vs. 2-3 weeks (manual) I/F controller IP Motion-detection IP 10x+ productivity increase 20% better quality of results 5x-10x faster, better verification Cadence Design Systems, Inc..
14 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Cynthesizer, Incisive, Encounter, Conformal, and the Cadence logo are trademarks or registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
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Functional Programming in Hardware Design Tomasz Wegrzanowski Saarland University Tomasz.Wegrzanowski@gmail.com 1 Introduction According to the Moore s law, hardware complexity grows exponentially, doubling