Silicon Labs. Timing Solutions for Xilinx FPGAs. Timing Simplified
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1 Silicon Labs Timing Solutions for Xilinx FPGAs Timing Simplified Silicon Labs offers a broad portfolio of frequency flexible timing products that enable hardware designers to simplify clock generation, distribution, and jitter attenuation. The portfolio includes: synchronizers attenuating clocks generators buffers PCIe clocks and buffers Oscillators (XO/VCXO) Silicon Labs clocks use proprietary DSPLL and MultiSynth technologies to generate any combination of frequencies with ultra-low jitter, enabling best-in-class clock tree integration. buffers provide low-jitter, low-skew clock distribution with integrated format/voltage level translation. PCIe clocks/buffers combine Gen 1/2/3/4 compliance with on-chip series termination, simplifying design. XO/VCXOs are factory-customizable to any frequency, with samples available in one to two weeks. Oscillators Any frequency up to 1.5 GHz -low jitter: 80 fs RMS Short lead times: 1-2 weeks (samples) s Any-frequency, any-output -low jitter: 90 fs RMS tree on a chip replaces clocks and XOs Integrated format/level translation -low additive jitter: 50 fs RMS PCI Express Gen 1/2/3/4 compliant s/ Sync Any frequency, any output -low jitter: 90 fs RMS tree on a chip replaces clocks, XOs, VCXOs
2 Recommended Timing Solutions vs Xilinx Protocol Xilinx Silicon Labs Virtex Kintex Artix Zynq XO/VCXO Buffer Gen Atten scale+ Band (MHz) Refclk TJ rms max (fs) Si51x Si59x Si54x Si533xx Si532x Si534x/8x CEI-6G-SR/LR CEI-11G-SR CEI-28G-VSR BASE-X (GbE) GBASE-R GBASE-KR CPRI 10G various CPRI 12G various CPRI 24G various CAUI CAUI Fibre Ch 8G, 16G Fibre Ch 32G GPON OTN (OTU/EPON) JESD204B various Interlaken 6G Interlaken 10G PCI Express Gen3 various 1000 PCI Express Gen4 various 500 RXAUI/DXAUI
3 Recommended Timing Solutions vs Xilinx Protocol Xilinx Silicon Labs Virtex Kintex Artix Zynq XO/VCXO Buffer Gen Atten scale+ Band (MHz) Refclk TJ rms max (fs) Si51x Si59x Si54x Si533xx Si532x Si534x/8x SGMII/QSGMII QPI Intel 200 SAS/SATA 6G SAS/SATA 12G SDI 3G, 6G 0.1-F/2 800 SDI 12G 0.1-F/2 400 SFI SFI RapidIO-1, -2, RapidIO SONET/SDH OC-48 SONET/SDH OC-192 XAUI 10GBASE-X XLAUI (40GbE)
4 Xilinx Phase Noise Mask Requirements GTY Transceiver XO VCXO Buffer 10 khz -112 dbc/hz -132 dbc/hz -129 dbc/hz -132 dbc/hz -140 dbc/hz -136 dbc/hz -126 dbc/hz -136 dbc/hz -137 dbc/hz 100 khz -128 dbc/hz -151 dbc/hz -134 dbc/hz -142 dbc/hz -150 dbc/hz -141 dbc/hz -132 dbc/hz -141 dbc/hz -145 dbc/hz 1 MHz -145 dbc/hz -160 dbc/hz -145 dbc/hz -148 dbc/hz -154 dbc/hz -150 dbc/hz -132 dbc/hz -154 dbc/hz -150 dbc/hz Xilinx Zynq GTH Transceiver XO VCXO Buffer 10 khz -111 dbc/hz -132 dbc/hz -129 dbc/hz -132 dbc/hz -140 dbc/hz -136 dbc/hz -126 dbc/hz -136 dbc/hz -137 dbc/hz 100 khz -130 dbc/hz -151 dbc/hz -134 dbc/hz -142 dbc/hz -150 dbc/hz -141 dbc/hz -132 dbc/hz -141 dbc/hz -145 dbc/hz 1 MHz -136 dbc/hz -160 dbc/hz -145 dbc/hz -148 dbc/hz -154 dbc/hz -150 dbc/hz -132 dbc/hz -154 dbc/hz -150 dbc/hz
5 Xilinx Phase Noise Mask Requirements scale GTY Transceiver XO VCXO Buffer 10 khz -112 dbc/hz -132 dbc/hz -129 dbc/hz -132 dbc/hz -140 dbc/hz -136 dbc/hz -126 dbc/hz -136 dbc/hz -137 dbc/hz 100 khz -128 dbc/hz -151 dbc/hz -134 dbc/hz -142 dbc/hz -150 dbc/hz -141 dbc/hz -132 dbc/hz -141 dbc/hz -145 dbc/hz 1 MHz -145 dbc/hz -160 dbc/hz -145 dbc/hz -148 dbc/hz -154 dbc/hz -150 dbc/hz -132 dbc/hz -154 dbc/hz -150 dbc/hz scale GTH Transceiver XO VCXO Buffer 10 khz -111 dbc/hz -132 dbc/hz -129 dbc/hz -132 dbc/hz -140 dbc/hz -136 dbc/hz -126 dbc/hz -136 dbc/hz -137 dbc/hz 100 khz -130 dbc/hz -151 dbc/hz -134 dbc/hz -142 dbc/hz -150 dbc/hz -141 dbc/hz -132 dbc/hz -141 dbc/hz -145 dbc/hz 1 MHz -136 dbc/hz -160 dbc/hz -145 dbc/hz -148 dbc/hz -154 dbc/hz -150 dbc/hz -132 dbc/hz -154 dbc/hz -150 dbc/hz For more information, visit silabs.com/timing
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