A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design

Transcription

1 A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design Ahmed Amine JERRAYA EPFL November 2005 TIMA Laboratory 46 Avenue Felix Viallet Grenoble CEDEX, France

2 The SoC Era Challenges SoC: put on a chip what we used to put on one or several boards (ASIC, CPU, Memories, Analog/RF, MEMS, ) Facts: g g 90% of new ASICs already include a CPU in 130nm. Multimedia, network processors, mobile terminals and game applications are already multiprocessors. Fundamental changes: g g g SoC is different from ASIC SoC is different from SW SoC requires abstract HW-SW interfaces to allow fast integrations. Challenges: g Generic SoC platform (programmable, reconfigurable,...) g Specific SoCs using standard IP with specific interconnect. EPFL,

3 Generic SoC Platform vs. Application-Specific MPSoC Example: The GSM History/Roadmap 1986 Rack in a van 1990 PCB 1995 Chip set in a hand-set 2002 SoC: Specific HW + CPU executing SW 2006 SW component on a generic platform, e.g. Nomadic (ST) Same roadmap for game computers, MP3, STB, NP, DVD EPFL,

4 Why SoC Design is Needed Applications Entertainment Security Networking Model terminal Productivity enhancements Example: MPEG2 encoding 2000x1000 frame Full motion search 128x128 search window 32 TIPS (TERA instruction per second) All software: RISC CPU, 1Ghz SoC Solution: 4 embedded specific CPU 200 Mhz EPFL,

5 The key SoC design Issue: HW/SW Gap Different Concepts to Abstract Interfaces g g HW communicates through wires. SW communicates through APIs The gap: SW model hides a CPU. HW-SW interfaces includes HW, SW and CPU HW Component Par x<= 0010 WIRES Rest of the system GAP SW Component foo Read (x) API Rest of the system EPFL,

6 Outline Defining HW-SW Interfaces HW-SW Discontinuities The Service Dependency Graph (SDG) Model Building Custom HW-SW Interfaces Application example EPFL,

7 Defining HW-SW Interfaces Application SW Designer: A set of system calls used to hide the underlying execution platform. Also Called Programming Model HW designer: A set of registers, control signals and more sophisticated adaptors to link CPU to HW subsystems. System SW designer: Low level SW implementation of the programming Model for a given HW architecture. CPU is the ultimate HW-SW Interface Sequential scheme assuming HW is ready to start low level SW design SOC requirements g g Abstracts both HW and SW in addition to CPU HW-SW interfaces tradeoff Sequential SW program Call HW (x, y, z) API SW Adaptation CPU (local Architecture) HW-SW CPU Interfaces CTRL HW-Adaptation Start done x y z HW function wait start data x y z EPFL,

8 HW/SW Interfaces Abstraction API Higher level OS level HAL level ISA level Wires RTL level BCA level TLM level Application HW software modules Abstract HW-SW Interfaces HW modules HdS fifo write... comm. cxt. sched.... system write reg drivers CPU subsystem CPU CPU memory Memory BUS Bridge other periph. Different Abstraction Levels for Both HW and SW Key issue: a unified model to represent CPU + SW + HW Key benefit: Formal reasoning, optimization partitioning and early validation of HW-SW interfaces. EPFL,

9 Outline 1. Defining HW-SW Interfaces 2. HW-SW Discontinuities 3. The Service Dependency Graph (SDG) Model 4. Building Custom HW-SW Interfaces 5. Application example EPFL,

10 Classical SW design flow to interface HW Programming Model: Abstract HW at Different level Discontinuities: Application Architecture Programming Model (API) Compilation: Generally ignore the CPU environment (Interrupts, Complex I/O) Sys.lib: adapt for different HW MMAP: Adapt to different CPUmemory architecture User.lib: to make the flow efficient for the application Sys.lib Program + API Calls Compiler Code+Calls Linker Executable Code MMAP User.lib EPFL,

11 HW/SW Interfaces in Classical SoC Design Flow System specification is a functional architecture: functional modules using specific programming models connected through abstract Interconnect Architecture implementation: heterogeneous components and sophisticated HW/SW interfaces HW/SW interfaces g Different Models (HW, SW, CPU) g Separate Design g Not efficient trade-off What is needed: A Unified Model for HW/SW Interfaces Codesign Virtual Virtual Processor Processor Virtual SW component Processor SW task 1 System Specification SW task 2 Virtual Virtual IP IP HW Virtual component IP HW block 1 HW block 2 Execution environment (e.g. TLM Cosimulation) SW components (Tasks) SW interface sub-system (SW w rapper) CPU sub-system HW interface sub-system (HW w rapper) API SW comp. API CPU API CPU. Basic SW interface component Basic HW interface component API HW comp. API netw ork Basic Mixed component API netw ork C ommunication interconnect ( e.g. NoC) HW component HW interface sub-system (HW w rapper) EPFL,

12 Existing HW-SW Integration Technologies Custom HDS generation for existing HW L. Gauthier, L. Benini, D. Gajski,... Custom CPU generation for specific SW Tensilica, ARC, Target,... Rest of the CPU Subsystem and HW are not handled API Custom HDS Generation Generic HDS Architecture Specification SW Program ASIP Generation Generic CPU Constraints API Custom HDS Executable SW Application Specific CPU EPFL,

13 Key Innovation to Higher Level HW/SW Interface Abstraction: from CPU to SW Execution Subsystem Application HW Software modules + Hardware HW-SW Dependent interfaces SW to be abstracted Hardware Hardware HW platform CPU HW & inf. to CPU HW Hardware modules API Wires or abs. channels Application HW software modules Abstract SW Execution engine Boot TaskMgr CPU MemBank (Mem) Ctrl Hardware interconnects Abstract comm. channels Traditional view of SoC CPU is HW-SW interface. SW validation assumes HW ready. SoC Model with Abstract HW-SW Interfaces Separate HW and SW design Better HW & SW reuse. Unified Model to abstract HW/SW Interfaces models HW, SW and CPU Allows new HW/SW architecture trade-off. EPFL,

14 Outline 1. Defining HW-SW Interfaces 2. HW-SW Discontinuities 3. The Service Dependency Graph (SDG) Model 4. Building Custom HW-SW Interfaces 5. Application example EPFL,

15 Service Dependency Graph Model Goal: adapting different interfaces Service Dependency Graph (SDG) Interface Component: g atomic unit that provides/requires services Previous Works Protocol stack optimization [Zitterbart92] Application specific OS Generation [Gauthier 1999] Subsystem A Execution environment Interface component wait_event Service dependency graph INTERRUPT_MANAGER memory_get block unblock interrupt EPFL,

16 Abstract Interface Interface is represented as 2 sets of logical ports connected through a SDG Logical Ports May be hierarchical and hold (provide) a list of services Interface Element Entity that provides(implements) and/or requires services May be HW, SW, Functional or Mixed HW/SW Service Defines a function or communication primitive Edges define the dependency relation between logical ports or interface elements and services. E1 Subsystem API P1 P1 S1 S5 Ab stract interface Requires Service PN PM E2 SSP S6 EEP Execution environment API Subsystem Port Interface element Service Provides Service SAP Port Access Execution environment Port EPFL,

17 SDG Combining HDS and CPU subsystem Application software switch_banks MEMORY_DRIVER wait_event INTERRUPT_MANAGER Hardwaredependent software controller_access memory_put memory_get MEMORY_IO ISA (e.g. load/store) block unblock interrupt (other part of HW/SW interface) MUITI-BANK MEMORY CONTROLLER CPU CPU subsystem mem_put bus_access mem_get bus_access bus_access MEMORY BANK (1 & 2) BUS NETWORK INTERFACE p2p_put p2p_get p2p_put p2p_get Hardware EPFL,

18 Outline 1. Defining HW-SW Interfaces 2. HW-SW Discontinuities 3. The Service Dependency Graph (SDG) Model 4. Building Custom HW-SW Interfaces 5. Application example EPFL,

19 Basic Concept: Composing Interfaces Component services Abstract interface services Execution environment Abstract interface g Required/Provided services g Control and Synchronization services g Parameters Interface sub-system Design g User-extensible library g Services matching g Code specialization Component Interface component library MPI channel Data conv. ARM7 boot I/O driver Scheduler Unix IPC Interface sub-system composition Works for HW, SW, Functional and CPU subsystems at Different abstraction levels send send ISR Sched. I/O write IT Execution environment EPFL,

20 SB-Colif: Application with abstract Interfaces Specification EPFL,

21 Library of Interface Components EPFL,

22 Application/Architecture with Abstract Interfaces Interface Generation Flow HW/SW interface generation tool Application/Architecture with explicit Interfaces Library Code selector Code generator Code integrator Validation/ Design EPFL,

23 Outline 1. Defining HW-SW Interfaces 2. HW-SW Discontinuities 3. The Service Dependency Graph (SDG) Model 4. Building Custom HW-SW Interfaces 5. Application example EPFL,

24 Application Example: MPEG4 F n (current) I P Motion Estimate Motion Compensate DCT Quant VLC Coded Stream Input F n-1 (ref.) Transform Module Trans.1 Trans.2 Trans.3 Trans.4 DMA Enco der Architecture design Motion Prediction Comb iner P I IDCT Functional model HW (Input) Interface HW (Comb iner) IQuant Interface HW (DMA) Interface DMA Encoder Module SW (P1..4) Interface Abstract architecture model SW (Pvlc) Interface HW/SW Interfaces to be designed EPFL,

25 MPEG4 Architecture with Application Specific HW-SW Interfaces Application software: encoder module taskvlc::task_behavior(), SW Execution Hardware-dependent software get_bank_address(), wait_event(), Subsystem SRAM 1 Ctrl CPU subsystem Hw Pvlc NI Application software: transform module task1::task_behavior(), Hardware-dependent software switch_banks(), wait_event(), SRAM SRAM Ctrl CPU subsystem SW Execution Subsystem P1..4 Hw NI 2 DMA Video stream Input Combiner Coded Stream EPFL,

26 Service Dependency Graph for SW Hardwaredependent software CPU subsystem 1 2 EPFL,

27 Perspectives: HDS-CPU Codesign, New Design/Synthesis Area SW API Abstract HW-SW interfaces HW interface HW HDS/CPU SS partitioning API HDS specification ISA ISA CPU subsystem specification HW interface Custom HDS design Custom CPU SS design SW API Custom HDS Custom CPU-SS HW interface HW SDG to represent Abstract Interfaces, CPU and HDS CPU subsystem may require sophisticated architecture in addition to CPU. HW-SW trade-off. EPFL,

28 Conclusions Classical design separates HW and SW interfaces SoC design requires to abstract CPU in addition to both HW and SW interfaces. Service dependency Graph is a working solution for HW/SW Interfaces abstraction Perspectives HW-SW interfaces codesign HW/SW tradeoff between HdS and CPU Formal reasoning and synthesis EPFL,

29 Thank You EPFL,

30 HW-SW interfaces architecture SW Application API HDS CPU subsystem Bus Adaptation HW-SW Interfaces Design Early DA COSY, Coware I SW Application API Fixed HDS library model Fixed CPU Bus Fixed HW architecture Second Generation Gauthier, Gajski, Benini SW Application API Custom HDS Fixed CPU SS Bus Fixed HW adaptation Next Generation HW-SW interfaces codesign SW Application API Custom HDS + CPU HW subsystem HW subsystem HW subsystem HW subsystem "HW-SW interfaces" includes 3 layers: HDS, CPU, HW Use of predesigned layers Use of custom HDS through personalization of a generic HDS Generic CPU but fixed Use of a custom adaptation through unified HDS-CPU subsystem representation model EPFL,

31 A Simple Application Example SW Abstract HW/SW Interfaces Input DMA (HW) Output EPFL,

32 Mixed Level HW/SW Interfaces SW Boot MemBank HW/SW Interfaces TaskMgr CPU (Mem) Ctrl Input DMA (HW) Output EPFL,

33 f 3 HW-SW Interfaces abstraction Levels f 1 f 2 HW/SW partitioning (Abstract Decomposition/mapping) (TLM: Abstract HW/SW Interfaces) Embedded software f 1 f 2 Platform API Abstract SW execution model Interconnect API Interconnect Embedded software f 1 f 2 Platform API Hardware f 3 HW interfaces (Abstract communication) Hardware f 3 Comm. Protocol & synchronization Interconnect API HW/SW communication protocol synthesis Embedded software f 1 f 2 Platform API HW/SW Interconnect synthesis (RTL) Embedded software f 1 f 2 Any intermediate level HW interfaces between TLM and RTL? SW adaptation CPU subsystem HW adaptation (MPI: Abstract Interconnect) Hardware f 3 HW interfaces Communication protocols Interconnect Hardware f 3 HW adaptation HW/SW Interfaces codesign EPFL,

34 Intermediate levels between TLM and RTL TLM Messages MPI More IMPLICIT OS Organisation Local CPU SS Architecture CPU implementation Implicit : CPU SS organization g SystemC 3.0: SW Native, BFM interface or CPU SS simulation Physical adressing All Explicit Implicit CPU organization g BCA: SW Bin, BFM interface or CPU ISA simulation Implicit Physical addressing (MMAP, Booting address, ) g MAXSIM: SW Bin, CPU ISS cycle accurate with explicit DATA Memory All explicit g Bin SW, RTL CPU + RTL HW + Physical memory EPFL,