A Methodology for NoC

Transcription

1 OCCN On-Chip Communication Architecture OccN A Methodology for NoC AST Grenoble Marcello Coppola

2 Outline SoC today NoC OCCN Case study Conclusion

3 Soc Today: A Variety of Networks & Terminals Ad-Hoc-Net s WLAN 2.5 G, 3G, 4G GPS DVB-S BASE STATION

4 Camera Display MP-SoC architecture: AMBA based Flash/ROM SRAM SDRAM ROM/ SRAM S S MPEG4 CODEC S M EDRAM EDRAMC S S S S LCD CTRL S M DPRAM MBX S S EMI S S SDRAM CTRL S S S S ROM/ SRAM S I Cache X SRAM PMC ST120 CORE DMC I SRAM Y SRAM Bus Switch AHB-M AHB-S AHB-M APB i/f DMA i/f Comunication Network APB Bridge M DMA Display AHB Video AHB ARM9 AHB ST120 AHB APB Bridge M I SRAM ARM926EJ-S CORE MMU D SRAM I Cache D Cache ST120 DMA GSM CYPHER ST120 ITC ST120 CTRL ST120 Timer WCDMA MODEM ST120 tightly coupled peripherals AUDIO I/f TDMA Mgt RF I/f MMC I/f USB I2S/PCM Shared peripherals ARM ITC Timers Watchdog RTC Clock Controller PLL - Oscillator UARTs ARM9 peripherals GSM TIME I2Cs SSPs GPRS CYPHER SIM I/f ADC GPIOs USIM I/f

5 Or.STBus based Type 2 MEM Type 2 Initiator P bits STBus P bits ST Bus P bits STBus N bits Type 2 MEM Type 2 Initiator P bits STBus P bits Node Y Type 2 Initiator P bits Type 2 Initiator P bits STBus P bits STBus P bits P Bits Type 2 STBus P bits STBus P bits Type 2 P-N Conv Type 2 N-P Conv STBus N bits STBus N bits Node Z N Bits Type 2 STBus N bits Type 2/ Type 1 Conv ST Bus N bits Type 2 Initiator N bits Type 2 Initiator N bits STBus N bits STBus N bits Type 1 REGS

6 Architecture evolution: from SoC to NoC System on a chip Programmable computation Hardwired interconnectivity Partially distributed storage

7 NoC I/O PE PE PE On-Chip Communication Architecture SE PE=Processing Element I/O=input/output SE=Storage Element

8 PE,I/O,SE SE PE Memory Controller I/O Motor control ASIC 3-phase controller A/D Timer PWM

9 Communication Centric Methodology

10 OCCN : methodology for communication modeling Generic communication-centric design methodology based on C++ and SystemC PE OCCN addresses high level performance modeling issues such as speed, latency and power estimation modeling productivity model portability simulation speed-up OCCN is an on-going research activity between several R&D organizations PE PE On-Chip communication architecture PE

11 OCCA PE PE OCCN STBUS on-chip communication architecture SE I/O

12 OCCN Conceptual Model Sw Adaptation OCCN Conceptual Model Application Layer Application API Adaptation Layer Hw Adaptation Communication API NoC Communication Layer

13 What is OCCN? OCCN aims at IC modeling, providing a real objectoriented methodology based on a C++ library and a fully documented design flow based on SystemC 2.0 User Model SystemC 2.0 Library OCCN Library SystemC 2.0 Scheduler

14 OCCN Focus Source: ARM

15 OCCN core: the PDU Protocol = syntax + semantics syntax = PDU semantics = how the PDU are exchanged The PDUs exchanged have two parts: a header also known as the Protocol Control Information (PCI) a payload also known as a Service Data Unit (SDU) Several operators are defined for handling protocol operations

16 PDU Examples 8 bits Pdu<char> p1; P T Data Struct DSLINK_token {unsigned int P:1; unsigned int T:1}; Pdu<DSLINK_token,char> p2; occn_hdr(pk1,p)=1; pk1= a ;

17 Generic representation of a connection Any connection of a module to the communication node (network) is based on 2 sets of PDU Pdu<uint32,PCIRequest> Pdu<uint32,PCIResponse> The PCI sets are described thanks to C/C++ structures. They are defined according to the bus specification and thus are specific to a model. For instance it will be different for an AHB model and an STBUS model IP (module) request Requestl PDU response PDU Response OCCN Struct { bool Request; unsigned char Opcode; bool Lock; } PCIControl

18 OCCN: communication SystemC based Interfaces Simple Message Passing API Transmit port a process Module 1 Channel port b Receiver process Module 2 Pdu< >* send(pdu< >* p, sc_time& time_out=-1); int trysend(pdu< >* p); Pdu< >* receive(int ack_time, sc_time& time_out=-1); Pdu< >* receive(sc_time& ack_time, sc_time& time_out=-1); Pdu< >* receive(sc_time& time_out=-1); void reply(pdu< >* p=0);

19 OCCN core : API semantic send (Pdu) Or trysend(pdu) Time Module A Time Module B trysend end Pdu = receive( ) Send( ) wake up reply( )

20 OCCN core : protocol state machine centralized PE send receive SE Clock allows synchronous and asynchronous communication modeling For synchronous com, PEs don t need to be connected to the clock signal

21 Performance measurement with Grace XY graph, XY charts, pie charts, polar, and fixed graphs. User-defined scaling, ticks, labels, symbols, line styles, fonts, colors. Merging, validation, cumulative average, curve fitting, regression, filtering, DFT/FFT, cross/autocorrelation, sorting, interpolation, integration, differentiation... Internal language, and dynamic module loading (C, Fortran, etc). Hardcopy support with PS, PDF, GIF and PNM formats.

22 Message passing oriented communication OCCN framework keypoints Protocol state machine centralized Generic structure for communication node PE request PDU response Communication Optimized physical transfer PDU Protocol state PE Synchronous or asynchronous communication with no simulation overhead machine System performance metrics Dynamic number of bound PE

23 MP SoC architecure main() { sc_clock my_clock(10, SC_NS); PE pe1, pe2; SE se; NoC occa(); PE1 PE2 } occa.clk(my_clock); pe1.port(occa); pe2.port(occa); se.port(occa); occa.set_address_range(&se1.port,0x100,0x500); occa.set_priority(&pe1.port, 2); occa.set_priority(&pe2.port, 5); sc_start(-1); NoC Target 0x100-0x500

24 OCCN: PE code example #include producer.h producer::producer(sc_module_name name) : sc_module(name) {SC_THREAD(read);} void producer::read() { char c; Pdu<char>* msg; while (cin.get(c)) { msg = new Pdu<char>; // producer sends c *msg = c; out.send(msg); } } // after the send the msg is not usable Protocol inlining: protocol is automatic generated

25 A Wide Variety of Linux Devices

26 Case study: Embedded Linux BSP for ST220 Linux BSP Kernel+drivers: ~ bundles (> instructions) Elf Linux Boot load in ext memory (3.5Mb) PE architecture D$/I$ Cache, Timer, Intrp Ctrl, Reg., etc. Simulation environment SystemC + OCCN + Models: compilation -O3 Linux version (Red Hat ) with Pentium 4 a 2.4 GHz, 512 Kb cache, 1 Gb RAM

27 Configuration 1: ISS Standalone/SystemC

28 Configuration 2: No bus-extmemory (no wait/delay) MailBox Memory

29 Configuration 3: NoC Platform OCCN On-Chip Communication AMBA AHBArchitecture MailBox Memory

30 Linux Boot: One ST220 IPS SEC ISS (StandAlone) ISS (systemc) No bus EXTMEM (no wait) No bus EXTMEM (delay 10ns) STANDARD BUS AHB BUS

31 Memory Map for 4 ST220 0xFFFFFFFF Boot 4 Boot 3 Boot 2 0x Boot 1

32 Linux Boot: for ST220 IPS SEC ISS (systemc) No bus EXTMEM (no wait) No bus EXTMEM (delay 10ns) STANDARD BUS AHB BUS

33 Conclusion 1/2 OCCN based on SystemC methodology open & flexible API simulation speed-up reusability productivity communication architecure exploration Similar work: Gigascale Silicon Research Center (GSRC) effort Princeton University: MESCAL Project Modern Embedded Systems Compilers Architectures and Languages Princeton and UC Berkeley

34 Conclusion 2/2 Research Activity funded in Medea Public part Univ. of Bologna Univ. of Roma Univ. of Ancona

35 Thank You and Contributing to OCCN