ProgrammingFPGAs. Dr. Vlassis Petousis. How to program FPGAs without VHDL knowledge. Ruđer Bošković Institut(RBI)
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1 ProgrammingFPGAs usinglabview How to program FPGAs without VHDL knowledge Dr. Vlassis Petousis Ruđer Bošković Institut(RBI)
2 Outline 1. Implementing a Boolean function in LabVIEW FPGA on the Xilinx SPARTAN Boards (LAB 01). 2. Embedding VHDL code in a Xilinx SPARTAN FPGA (LAB 02). 5/11/2011 2
3 LabVIEW+ Basic FPGA F = (A+B)CD Implementing Logic on FPGA 5/11/2011 3
4 LabVIEW FPGAProject We have to create an Empty Project 5/11/2011 4
5 LabVIEW FPGA Project Right click on My Computer in the Project Explorer view. We select New and then Targets and Devices. 5/11/2011 5
6 LabVIEW FPGA Target New target or device 5/11/2011 6
7 LabVIEW FPGA I/O For this wehave to right click the FPGA Target 5/11/2011 7
8 LabVIEW FPGA I/O If we go back to the Project Explorer view we see the FPGA I/O that we have added. With this I/O we will implement an Exclusive-OR function. 5/11/2011 8
9 LabVIEW FPGA VI 1. The next step is the creation of a hardware program that runs on the Xilinx Spartan hardware target. 2. For this we do again a right mouse click on the FPGA target in the Project Explorer view. Select New VI 5/11/2011 9
10 LabVIEW FPGA VI We created : 5/11/
11 LabVIEW FPGA create Nodes We place 2I/O Nodes on the Block Diagram of the LabVIEWFPGA VI 5/11/
12 LabVIEW FPGAaddNodes To add another FPGA I/O. For this do a right click on the FPGA I/Oyou just filled with SW0. Select Add Element. 5/11/
13 LabVIEW FPGAaddNodes We can do the same to add another FPGA I/O 5/11/
14 LabVIEW FPGAexclusive OR Now we will as an example implement an exclusive-or Boolean function into the FPGA. From the Functions Palette select Programming Boolean and look for the Exclusive OR function. Place this one on the Block diagram. XOR Truth Table Input A B Output /11/
15 LabVIEW FPGAexclusive OR Wire the SW1 and SW0 FPGA I/O to the Exclusive-OR inputs. Wire the output of the function to LED0. 5/11/
16 LabVIEW FPGA While Loop When we implement the function like presented above the function will run only once. We would like to implement it that it runs continuously. For this we place a While Loop around it and we wire a Boolean False constant to the stop condition of this loop. The While Loop you find on the Functions Palette. 5/11/
17 LabVIEW FPGA While Loop 5/11/
18 LabVIEW FPGA Save as Now it is time to save ourvithat wecreated for the FPGA. Wedo this by selecting File Save As... in either the Front Panel or the Block Diagram. 5/11/
19 LabVIEW FPGA RunningVIs For starting the executing of this VI we have to press the Run arrow on either the Block Diagram or on the Front Panel. 5/11/
20 LabVIEW FPGARunningVIs LabVIEW does Generating Intermediate Files. This files will be send to the Xilinx Synthesis Tools. But this is not important for us as application developers. 5/11/
21 LabVIEW FPGARunningVIs LabVIEW starting the Compile Server. 5/11/
22 LabVIEW FPGA RunningVIs 5/11/
23 LabVIEW FPGARunningVIs When the Bitstream generation is complete message appears and the server status is set to Idle the Xilinx synthesis tools have done their job. 5/11/
24 LabVIEW FPGARunningVIs You get a Successful Compile Report where you can see the implementation details of your code. You have to Press Ok. 5/11/
25 LabVIEW FPGATarget Run After you have pressed the Ok button your VI starts running on the FPGA target. It is indicated on your screen by the black Run arrow. 5/11/
26 LabVIEW SPARTAN 3E Playing with the switches SW0 and SW1 on the SPARTAN starter board you will see they have an XOR function.the led LD0 will be ON when one of those switches is turned ON. The problem with this implementation is that when you stop thevi, the function is erased on the LabVIEWFPGA board. If you don t want this effect you can download this VI to the FLASH of the Xilinx SPARTAN starter board. 5/11/
27 LabVIEW SPARTAN 3E 5/11/
28 LabVIEW FPGAinto FLASH For implementing your VI into the FLASH on the SPARTAN Starter board you have to do some things. 1.Run when loaded to FPGA on. For this you have to go to Project Explorer. 2. Right Mouse click on your FPGA target. Select the Properties option. 5/11/
29 LabVIEW FPGA into FLASH Run when loaded to FPGA. Make sure you select this option. Then press the OK button. 5/11/
30 LabVIEW FPGA into FLASH 5/11/
31 LabVIEW FPGAinto FLASH We must recompile the VI because we made a change. Do this by going to the Project Explorer view. Click with the Right Mouse button on the FPGA VI you have created for this project. Select the Compile option. 5/11/
32 LabVIEW FPGAinto FLASH Wewill see that there are some previous steps executed. When the Successful Compile Report shows up you have to press the OK button. Now we will download it to the Flash. For this you have to go to the Project Explorer view and do a right mouse click on the FPGA VI you created. Then choosing the Download VI to Flash Memory option will start downloading it to the SPARTAN starter board flash. 5/11/
33 LabVIEW FPGAinto FLASH LabVIEW FPGA VI is downloaded to the Flash. 5/11/
34 Outline 1. Implementing a Boolean function in LabVIEW FPGA on the Xilinx SPARTAN Boards (LAB 01). 2. Embedding VHDL code in a Xilinx SPARTAN FPGA (LAB 02). 5/11/
35 Embedding VHDL in a FPGA LAB02 The first things we have skipped because it is the same as in. In this LABwe are going to create a parity checker. (Parity checking is a rudimentary method of detecting simple, single-bit errors in a memory system. In ncommunications, parity checking refers to the use of parity bits to check that data has been transmitted accurately. The parity bit is added to every data unit (typically 7 or 8bits) that are transmitted. The parity bit for each unit is setso that allbyteshave either an odd number or an even number of set bits). We will put LED0 of the Spartan3E Starter board on when the input ofthe checker system (by use of SW0, SW1, SW2 and SW3 ) has even bits. 5/11/
36 Step 1: Adding FPGA I/O LAB02 5/11/
37 Step 2: Creating the VI LAB02 Do a right mouse click on the FPGA Target in the Project Explorer. From the pull down menu select New => VI. 5/11/
38 Step 2: Creating the VI LAB02 On the block diagram of this VI we have to put a Timed Loop 5/11/
39 Step 2: Creating the VI LAB02 In this Timed Loop you have to place a HDL Interface Node 5/11/
![Step 2: Creating the VI LAB02 Now double click the HDL Node ; you will get the following screen: In the first screen we try to add the following 2 parameters: Name inp Direction in, Type TF [ ]](/docs-images/77/75573707/images/40-1.jpg "Length 4 Name outp Direction out Type TF. Length -- 1 st SET 2 nd SET Type Defines the data type of the parameter. LabVIEW displays only a subset of the data types supported in FPGA VIs.")
40 Step 2: Creating the VI LAB02 Now double click the HDL Node ; you will get the following screen: In the first screen we try to add the following 2 parameters: Name inp Direction in, Type TF [ ] Length 4 Name outp Direction out Type TF. Length -- 1 st SET 2 nd SET Type Defines the data type of the parameter. LabVIEW displays only a subset of the data types supported in FPGA VIs. Length Defines the size of the Boolean array if you select the Boolean array data type in the Type column. 5/11/
41 Step 2: Creating the VI LAB02 In the code screen we replace hdlnode (name of the entity) to even_parity. The field below architecture implementation of even_parity is has to been filled with the following VHDL rule: signal s1, s2, s3, s4, s5, s6, s7, s8: std_logic; 5/11/
42 Step 2: Creating the VI LAB02 The field below the VHDL keyword begin has to been filled with the following VHDL code: outp(0) <=((s1 or s2) or (s3 or s4)) or ((s5 or s6) or (s7 or s8)); s1 s2 s3 s4 s5 s6 s7 s8 <=(not inp(3)) and (not inp(2)) and (not inp(1)) and (not inp(0)); <=(not inp(3)) and (not inp(2)) and inp(1) and inp(0); <=(not inp(3)) and inp(2) and (not inp(1)) and inp(0); <=(not inp(3)) and inp(2) and inp(1) and (not inp(0)); <=inp(3) and (not inp(2)) and (not inp(1)) and inp(0); <=inp(3) and (not inp(2)) and inp(1) and (not inp(0)); <=inp(3) and inp(2) and (not inp(1)) and (not inp(0)); <=inp(3) and inp(2) and inp(1) and inp(0); enable_out<='1'; 5/11/
43 Step 2: Creating the VI LAB02 In the tab Execution Control check the option Single-Cycle Timed Loop Allowed and click the OK button. 5/11/
44 Step 2: Creating the VI LAB02 Now we place two FPGA I/O Node s on the block diagram of your VI. Build an array with SW0, SW1, SW2 and SW3 as inputs. We connect the output of this build array function to the input of the HDLNode called inp. Connect now LED0 to outp of the HDLNode. 5/11/
45 Step 3: Running the VI LAB02 Now go to the Project Explorer. Right mouse click on FPGA Target then select Properties. 5/11/
46 Step 3: Running the VI LAB02 Be sure to check in this window Run when loaded to FPGA before compiling the VI. 5/11/
47 Step 3: Running the VI LAB02 Go back to Project Explorer. Do a right mouse click on FPGA_VI_VHDL. Select Compiler and let the LabVIEW FPGA code compile. When the compilation completed go to Project Explorer and do a right mouse click on FPGA_VI_VHDL and select Download VI to Flash Memory 5/11/
48 LabVIEW FPGA Now you can pull out the USB cable out of the Xilinx Spartan3E board and press the PROG button on this board. You will see that the function is implemented in it. 5/11/
49 Take away home 1 st LabVIEWtoday is a very powerful tool in Science. 2 nd Contains an easy way to embed VHDL code in FPGA s. 3 rd Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Thank You for Your Attention 5/11/
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