In-Design and Signoff Pattern Detection and Fixing Flows for Accelerated DFM Convergence. Karthik Krishnamoorthy - DFM Design Enablement
|
|
- Denis Russell
- 6 years ago
- Views:
Transcription
1 In-Design and Signoff Pattern Detection and Fixing Flows for Accelerated DFM Convergence Karthik Krishnamoorthy - DFM Design Enablement 1
2 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 2
3 Company Highlights REVENUE ~6B* 25,000 2nd Largest Foundry Patents & Applications MORE THAN 250 Customers 18,000 Employees FAB LOCATIONS FAB CAPACITY Burlington East Fishkill Dresden Malta Singapore Trusted Foundry 300mm 200mm 200K 133K Wafers/Mo Wafers/Mo *Based upon analysts estimates
4 Global Manufacturing Capacity ~7M Wafers / Yr* East Fishkill, New York Malta, New York Burlington, Vermont Dresden, Germany Singapore TECHNOLOGY 90nm 22nm 28nm, 14nm 350nm 90nm 45nm 22nm 180nm 40nm CAPACITY IN WAFERS/MONTH Up to 14,000 (300mm) 40,000 (200mm) 60,000 (300mm) 60,000 (300mm) 68,000 (300mm) 93,000 (200mm) *200mm Equivalents
5 Process Platforms Dynamic Body-bias Ultra-low Voltage Operation 22nm FD-SOI 14nm FinFET Performance/Power Efficiency Global Manufacturing In Development 7nm High-volume Production Proven PPA 28nm nm Mainstream Solutions
6 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 6
7 GLOBALFOUNDRIES reference flow GLOBALFOUNDRIES DFM mandatory sign-off requirements are well integrated into the design environment DRC+: Litho hotspot detection and fixing DFM-POP: Silicon-validated Pattern OPtimization to enforce statistical yield improvement Current solutions relying on place & route heuristics to meet DFM requirements are limited and inefficient Requires several iterations and longer TAT for routing closure and sign-off Yield layout enhancements cannot be done manually due to the large number of patterns to optimize Performing GDS level changes is expensive and cumbersome for downstream flows DFM must be fast, integrated in the design and signoff flows, and provide automated fixing and optimization solutions 7
8 GLOBALFOUNDRIES reference flow DFM - DRC+ As design dimensions shrink in the advanced nodes, feature size has decreased faster than illumination wavelength Resolution Enhancement Techniques (RET) and Optical Proximity Correction (OPC) allow to improve the printability but in advanced technology nodes, proximity effects can cause variability of Critical Dimension (CD) DRC+ developed as a Super-Set of DRC, RET and OPC techniques, extended to the Design and Physical Verification space 8
9 GLOBALFOUNDRIES reference flow DFM - Pattern Optimization (DFM-POP) Traditional approach to fix In-design DRC+ hotspots Uses rip-up and re-route of design to fix hotspot violations Multiple iterations (> 5) required to converge / fix violations NO custom fixing guidelines provided in the pattern definitions Slower TAT as pattern library grows and design size increase DFM-POP flow advantages Performs In-Situ fixing of the hotspot patterns Very high fixing rate (> 85-90%) in 1st iteration Fixes are correct by construction by enabling patterns with custom fixing guidelines Faster TAT - converge to 100% fix solution in couple of iterations Before PM After PM using rip-up&re-route After PM using Fixing Guidance 9
10 GLOBALFOUNDRIES reference flow GLOBALFOUNDRIES DFM- POP flow Provides the framework to speed up the ECO Enabling fixing guidelines in the pattern definition Perform incremental pattern DRC-clean update Cadence LPA based auto fixing flow allows targeted fixing guidelines in the pattern library provided by foundry Cadence LPA based fixing flows are well integrated into the Innovus and Virtuoso Custom design platforms Placement Routing DRC+ / DFM-POP STA DRC / LVS Litho Sim Timing Closure ECO Physical Verification optional ECO
11 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 11
12 In-Design Pattern fixing flow Non-Integrated Flow Routed Design Export GDS (3 rd party tool) Litho/PM check Import litho HS markers GlobalDetailRoute (search&repair) Innovus/EDI DFM Flow Routed Design VerifyLitho (Integrated LPA) Fix guidelines VerifyLitho using ripup-reroute (optional) GlobalDetailRoute (search & repair) In-design pattern aware fixing improves the flow by removing extra step Additional steps at layout level (few hours) eliminates time-consuming loops after tape out LPA In-Design hotspot fixing greatly simplifies the task of handling mandatory DRC+ signoff criteria 12
13 In-Design Pattern fixing flow LPA tool based on TVL / squish topological pattern representation allows DRC+/DFM-POP pattern library definition with custom fixing guidelines TVL (Three Value Logic) Pattern Representation match occurs if: Key Region is fully covered/ Space is fully un-covered Shape edges must lie in the region between the Key and Space (i.e. within the Don t Care Region) squish topological pattern is: Topological representation: Textual bitmap of the pattern topology Dimensional information: X and Y_deltas representing the row/column sizes Optimization guidelines: targeted shape operation TVL pattern Squish pattern x_deltas=" " y_deltas= <overlay_scanline_range range_str="x1 y2 x2 y3" range_str="x5 y1 x6 y3 3-finger pattern 13
14 In-Design Pattern fixing flow LPA deck creation LPA deck defined based on TVL / squish deck pattern definitions Uses overlay_scanline / overlay_box to specify custom fixing guidelines Applied with verifylitho using squishhints Order of applying the fix guidelines TVL Squish Conf. setup Apply fixing guidelines first EDI/Innovus always starts with targeted fixing guidelines based on the order defined. If first guidelines fails, next one will be applied Localized reroute optional with ripandreroute GLOBALFOUNDRIES DRC+/DFM-POP LPA deck 14
15 In-Design Pattern fixing flow TVL pattern definition Overlay Box fixing guidelines M M X X WIDTH X 15
16 In-Design Pattern fixing flow Squish deck pattern definitions Overlay_scanline fixing guidelines X X X 16
17 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 17
18 In-Design LPA-based Autofix Both DRC+ and DFM-POP autofix flows based on LPA use the same built-in EDI/ Innovus command verifylitho 1st iteration: runs LPA and generates the hotspot information file (HIF) and targeted guidelines for autofix 2nd iteration: optionally runs traditional rip-up/reroute fixing for remaining hotspots The pattern fixing guidelines can be applied to both route and via shapes in the place & route database The LPA tool applies the fixing guidelines in the router database and ensures it is DRC clean EDI/INNOVUS Routed design Targeted fixing w/ guidelines Router Fixing (ripandreroute) Signoff 18
19 In-Design LPA-based Autofix LPA Techfiles enabled with the TVL overlay_boxes or squish hints can do the following Find and fix hotspots using the fixing guidelines set techfile <appropriate LPA techfile> ; # setup up techfile set dfmfixing::lpareplacedolocal 1 ; # setup up local fixing # fix with hints verifylitho routinglayersonly -techfile $techfile dir Results_1 mapfile mapfile streamoutoptions {-ouputmacros } guideline apply squishhints # find remaining and setup ripandreroute fixing verifylitho routinglayersonly -techfile $techfile dir Results_2 mapfile mapfile streamoutoptions {-ouputmacros } apply ripandreroute globaldetailroute # remove blockages foreach layer { M2 M3 C4 C5 C6 C7 K1 K2 } { deleterouteblock ${layer}_litho_repair } 19
20 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 20
21 LPA Innovus/Virtuoso Integration LPA engine is well integrated with both the Digital / Custom Design environment Provides flexible high-performance / capacity layout analysis and optimization Localized fixing using squish topological patterns 21
22 LPA Virtuoso Integration DRC+/DFM-POP LPA techfile can be invoked in Virtuoso environment seamlessly 22
23 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 23
24 Results: LPA In-Design Fix Hotspot repair with custom Fixing Guidelines Fix Guidelines Default
25 Results: Before and After LPA autofix DRC+ Fixing Results Before fixing After fixing with guidelines RULECHECK PM.Rule.C.21 = 3 (3) RULECHECK PM.Rule.lv2 = 17 (17) RULECHECK PM.Rule.lv2 = 1 (1) RULECHECK PM.Rule.21 = 1 (1) RULECHECK PM.Rule.lv2 = 1 (1) RULECHECK PM.Rule.C.21 = 1 (1) RULECHECK PM.Rule.lv2 = 2 (2) --- RULECHECK PM.Rule.C.21 = 1 (1) --- Line-end extension Size 2 sq. mm Hotspots Fixed Detection time (8 CPUs) Fixing time 1 st pass detection and fixing using guidelines (98%) 3m 55s 3m 20s 2 nd pass detection fixing using globaldetailroute 7 7 (100%) 3m 58s 3h 58m 25
26 Agenda GLOBALFOUNDRIES update GLOBALFOUNDRIES reference flow In-Design Pattern Fixing Flow In-Design Auto-Fix and Sign-Off Innovus / Virtuoso-DFM Integration Results Summary 26
27 Summary Current In-Design Pattern fix status In-Design pattern with targeted fixing guidelines deployed for 14nm / 22FDx nodes Automated pattern fixing LPA pattern fixing flow enables ~4X faster convergence than the traditional rip-up and reroute flow Fixes > 90% of the violations with the fixing guidelines in 1st iteration Ensures faster TAT for post-fix timing closure In-Design Pattern fix saves significant design cycle time 27
28 Authors GLOBALFOUNDRIES Fadi Batarseh, Ahmed Omran, Piyush Pathak, Uwe Paul Schroeder, Sriram Madhavan CADENCE Ya-Chieh Lai, Jason Sweis, Jac Paul Condella, Philippe Hurat Acknowledgements Haritez Narisetty Tamer Ragheb Ramya Srinivasan Tze Haw Liew Sumanth Prakash GLOBALFOUNDRIES Confidential 28
29 Thank you Disclaimer The information contained herein [is confidential and] is the property of GLOBALFOUNDRIES and/or its licensors. This document is for informational purposes only, is current only as of the date of publication and is subject to change by GLOBALFOUNDRIES at any time without notice. GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. Other product or service names are for identification purposes only and may be trademarks or service marks of their respective owners. GLOBALFOUNDRIES Inc Unless otherwise indicated, all rights reserved. Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES.
Pattern-based analytics to estimate and track yield risk of designs down to 7nm
DAC 2017 Pattern-based analytics to estimate and track yield risk of designs down to 7nm JASON CAIN, MOUTAZ FAKHRY (AMD) PIYUSH PATHAK, JASON SWEIS, PHILIPPE HURAT, YA-CHIEH LAI (CADENCE) INTRODUCTION
More informationIntroducing the FX-14 ASIC Design System. Embargoed until November 10, 2015
Introducing the FX-14 ASIC Design System Embargoed until November 10, 2015 Market Forces Are Driving Need for a New Breed of Semiconductor By 2019: Bandwidth Roughly one million minutes of video will cross
More informationPVS Interactive Short Locator: Establishing Efficiency and Predictability in the LVS Short Debug Process for Advanced SoC Design
: Establishing Efficiency and Predictability in the LVS Short Process for Advanced SoC Design ging SoC designs grows more challenging as process technologies shrink. The time required to run multiple iterations
More information2. TOPOLOGICAL PATTERN ANALYSIS
Methodology for analyzing and quantifying design style changes and complexity using topological patterns Jason P. Cain a, Ya-Chieh Lai b, Frank Gennari b, Jason Sweis b a Advanced Micro Devices, 7171 Southwest
More informationemram: From Technology to Applications David Eggleston VP Embedded Memory
emram: From Technology to Applications David Eggleston VP Embedded Memory 10,000 foot view What are we trying to achieve? 2 Memory is Know Remembering. Think Events 3 Memory is Code Persistence. Data State
More informationGF14LPP-XL AMS Reference Flow for FINFET Technology. Rajashekhar Chimmalagi Design Methodology April 5 th 2016
GF14LPP-XL AMS Reference Flow for FINFET Technology Rajashekhar Chimmalagi Design Methodology April 5 th 2016 Agenda 1 FinFET & FinFET Challenges 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules
More informationTaming the Challenges of Advanced-Node Design. Tom Beckley Sr. VP of R&D, Custom IC and Signoff, Silicon Realization Group ISQED 2012 March 20, 2012
Taming the Challenges of Advanced-Node Design Tom Beckley Sr. VP of R&D, Custom IC and Signoff, Silicon Realization Group ISQED 2012 March 20, 2012 The custom design community Designers ( Relaxed attitude
More informationDATASHEET VIRTUOSO LAYOUT SUITE GXL
DATASHEET Part of the Cadence Virtuoso Layout Suite family of products, is a collection of fully automated layout capabilities such as custom placement and routing, layout optimization, module generation,
More informationAccelerating 20nm Double Patterning Verification with IC Validator
White Paper Accelerating 20nm Double Patterning Verification with IC Validator Author Paul Friedberg Corporate Applications Engineering Stelios Diamantidis Product Marketing Abstract The emergence of Double
More informationAn Automated System for Checking Lithography Friendliness of Standard Cells
An Automated System for Checking Lithography Friendliness of Standard Cells I-Lun Tseng, Senior Member, IEEE, Yongfu Li, Senior Member, IEEE, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, and Jonathan
More informationDATASHEET VIRTUOSO LAYOUT SUITE FAMILY
DATASHEET The Cadence Virtuoso Layout Suite family of products delivers a complete solution for front-to-back custom analog, digital, RF, and mixed-signal design. It preserves design intent throughout
More informationIn-design DFM rule scoring and fixing method using ICV
In-design DFM rule scoring and fixing method using ICV Vikas Tripathi, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jason Khaw and Jonathan Ong Globalfoundries Singapore Pte. Ltd. Singapore www.globalfoundries.com
More informationVirtuoso Layout Suite XL
Accelerated full custom IC layout Part of the Cadence Virtuoso Layout Suite family of products, is a connectivity- and constraint-driven layout environment built on common design intent. It supports custom
More informationRevolutionizing RISC-V based application design possibilities with GLOBALFOUNDRIES. Gregg Bartlett Senior Vice President, CMOS Business Unit
Revolutionizing RISC-V based application design possibilities with GLOBALFOUNDRIES Gregg Bartlett Senior Vice President, CMOS Business Unit RISC-V: Driving New Architectures and Multi-core Systems GF Enabling
More informationEnabling An Interconnected Digital World Cadence EDA and IP Update. Jonathan Smith Director, Strategic Alliances June 1, 2017
Enabling An Interconnected Digital World Cadence EDA and IP Update Jonathan Smith Director, Strategic Alliances June 1, 2017 IoT Market Definition and Growth Estimates Large and widely varying Known: IoT
More informationComprehensive Place-and-Route Platform Olympus-SoC
Comprehensive Place-and-Route Platform Olympus-SoC Digital IC Design D A T A S H E E T BENEFITS: Olympus-SoC is a comprehensive netlist-to-gdsii physical design implementation platform. Solving Advanced
More informationDesigning into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications
Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications A Collaborative White Paper by RAMBUS and GLOBALFOUNDRIES W h i
More informationSynopsys Design Platform
Synopsys Design Platform Silicon Proven for FDSOI Swami Venkat, Senior Director, Marketing, Design Group September 26, 2017 2017 Synopsys, Inc. 1 Synopsys: Silicon to Software Software Application security
More informationTransforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry. Dr. Thomas de Paly
Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry Dr. Thomas de Paly October 06, 2009 Opportunity Meets Vision Vision To be the first truly global semiconductor foundry,
More information0.35um design verifications
0.35um design verifications Path end segment check (END) First check is the end segment check, This error is related to the routing metals when routing is done with a path. The finish of this path can
More informationConcurrent, OA-based Mixed-signal Implementation
Concurrent, OA-based Mixed-signal Implementation Mladen Nizic Eng. Director, Mixed-signal Solution 2011, Cadence Design Systems, Inc. All rights reserved worldwide. Mixed-Signal Design Challenges Traditional
More informationCollaborate to Innovate FinFET Design Ecosystem Challenges and Solutions
2013 TSMC, Ltd Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions 2 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges
More informationCredit Suisse European Technology Conference
Credit Suisse European Technology Conference Franki D Hoore Director European Investor Relations May 12, 2010 / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform
More informationEuropractice Cadence release. IC Package ASSURA 4.1 ASSURA 4.1 ASSURA 4.1
Release CTOS 14.2 Description Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier Assura(TM) Multiprocessor Option CCD Multi-Constraint Check Option Encounter (R) Conformal Constraint
More informationAccelerating China Semiconductor Industry with GlobalFoundries Smart Manufacture. Fisher Zhu, Director of China Marketing March 15, 2018
Accelerating China Semiconductor Industry with GlobalFoundries Smart Manufacture Fisher Zhu, Director of China Marketing March 15, 2018 GLOBALFOUNDRIES PROPRIETARY The GLOBALFOUNDRIES Story Building an
More informationOne-Shot DRC within a Fine-Grain Physical Verification Platform for advanced process nodes
One-Shot DRC within a Fine-Grain Physical Verification Platform for advanced process nodes Last updated: May, 2017 To meet the challenge of nano-scale, deep sub-wavelength processes, innovative One -Shot
More informationIntrusive Routing for Improved Standard Cell Pin Access
Intrusive Routing for Improved Standard Cell Pin Access Vishesh Dokania Prof. Puneet Gupta NanoCAD Lab Department of Electrical Engineering, UCLA MS Project Presentation March 10, 2017 Motivation Standard-cell
More informationCMP Model Application in RC and Timing Extraction Flow
INVENTIVE CMP Model Application in RC and Timing Extraction Flow Hongmei Liao*, Li Song +, Nickhil Jakadtar +, Taber Smith + * Qualcomm Inc. San Diego, CA 92121 + Cadence Design Systems, Inc. San Jose,
More informationEnabling DFM Flow Peter Rabkin Xilinx, Inc.
Enabling DFM Flow Peter Rabkin Xilinx, Inc. Open DFM Workshop San Jose CA v 9, 2006 2006 All Rights Reserved Fabless Litho-DFM Requirements Design Tolerance Req s Systematic & automated litho compliance
More informationidrm: Fixing the broken interface between design and manufacturing
idrm: Fixing the broken interface between design and manufacturing Abstract Sage Design Automation, Inc. Santa Clara, California, USA This paper reviews the industry practice of using the design rule manual
More informationAnalog, Mixed-Signal, and Advanced-Node Custom Design Scalability, Convergence and Throughput
Analog, Mixed-Signal, and Advanced-Node Custom Design Scalability, Convergence and Throughput Tom Beckley, Senior VP of R&D, Custom IC and Simulation Analog Semiconductor Leaders' Forum Seoul, Korea October
More informationVirtuoso - Enabled EPDA framework AIM SUNY Process
Virtuoso - Enabled EPDA framework AIM SUNY Process CADENCE, LUMERICAL, PHOENIX SOFTWARE Driven by our customers Cadence is the leader with Virtuoso custom design platform for electronics custom and mixed
More informationAdvanced multi-patterning and hybrid lithography techniques. Fedor G Pikus, J. Andres Torres
Advanced multi-patterning and hybrid lithography techniques Fedor G Pikus, J. Andres Torres Outline Need for advanced patterning technologies Multipatterning (MP) technologies What is multipatterning?
More informationECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017
ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017 In this MP, you will use automated tools to synthesize the controller module from your MP2 project into
More informationExpert Layout Editor. Technical Description
Expert Layout Editor Technical Description Agenda Expert Layout Editor Overview General Layout Editing Features Technology File Setup Multi-user Project Library Setup Advanced Programmable Features Schematic
More informationManufacturing Challenges and their Implications on Design
Manufacturing Challenges and their Implications on Design Phiroze Parakh, Ph.D 45nm/32nm Design Challenges MANUFACTURING VARIATIONS PROCESS & DESIGN VARIATIONS LARGE DESIGNS LOW POWER The Evolution of
More informationHigh Quality, Low Cost Test
Datasheet High Quality, Low Cost Test Overview is a comprehensive synthesis-based test solution for compression and advanced design-for-test that addresses the cost challenges of testing complex designs.
More informationDeep Sub-Micron Cache Design
Cache Design Challenges in Deep Sub-Micron Process Technologies L2 COE Carl Dietz May 25, 2007 Deep Sub-Micron Cache Design Agenda Bitcell Design Array Design SOI Considerations Surviving in the corporate
More informationPhysical design and mask synthesis considerations for DPT
Physical design and mask synthesis considerations for DPT Kevin Lucas, Chris Cork, John Hapli, Alex Miloslavsky Synopsys Vincent Wiaux, Staf Verhaegen IMEC Double Patterning pitch splitting 1 st trench
More informationCadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics
Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics Introduction This tutorial describes how to generate a mask layout in the Cadence Virtuoso Layout Editor. Use of DIVA
More informationLaker and Calibre RealTime, an OA Integration Success Story
Silicon Integration Initiative Laker and Calibre RealTime, an OA Integration Success Story Rich Morse, Marketing & EDA Alliances Manager, SpringSoft Anant Adke, Director of Engineering, Design to Silicon
More informationDesign Compiler Graphical Create a Better Starting Point for Faster Physical Implementation
Datasheet Create a Better Starting Point for Faster Physical Implementation Overview Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical streamlines the flow for
More informationRecent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability Chung-Wei Lin 1, Ming-Chao Tsai 2, Kuang-Yao Lee 2, Tai-Chen Chen 1, Ting-Chi Wang 2, and Yao-Wen Chang 1 1
More informationIntroducing the 22FDX. 22nm FD-SOI Platform. from GLOBALFOUNDRIES
Introducing the 22FDX 22nm FD-SOI Platform from GLOBALFOUNDRIES March 2016 Introduction Selecting a next generation technology platform for your new product is a critical decision. Product requirements
More informationAMS DESIGN METHODOLOGY
OVER VIEW CADENCE ANALOG/ MIXED-SIGNAL DESIGN METHODOLOGY The Cadence Analog/Mixed-Signal (AMS) Design Methodology employs advanced Cadence Virtuoso custom design technologies and leverages silicon-accurate
More informationOpenDFM Targeting Functions. Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair
OpenDFM Targeting Functions Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair Targeting Design Drawn Shapes Mfg. Targeting Targeting takes the Drawn Shapes provided by the layout
More informationSilicon Photonics Scalable Design Framework:
Silicon Photonics Scalable Design Framework: From Design Concept to Physical Verification Hossam Sarhan Technical Marketing Engineer hossam_sarhan@mentor.com Objective: Scalable Photonics Design Infrastructure
More informationPrepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology
Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features
More informationDFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group
I N V E N T I V E DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group Moore s Law & More : Tall And Thin More than Moore: Diversification Moore s
More informationJoe Civello ADS Product Manager/ Keysight EEsof EDA
Joe Civello 2018.01.11 ADS Product Manager/ Keysight EEsof EDA 3D Layout Viewing directly from the Layout Window 3D Editing & Routing PCB & IC/Module Design Dramatically Improved Visual Inspection Simplified
More informationDriving Leading Edge Microprocessor Technology
Driving Leading Edge Microprocessor Technology Dr. Hans Deppe Corporate Vice President & General Manager AMD in Dresden AMD Overview A leading global supplier of innovative semiconductor solutions for
More informationDriving Semiconductor Industry Optimization From. Walden C. Rhines. CHAIRMAN & CEO Mentor Graphics Corporation
Driving Semiconductor Industry Optimization From U.S.-Taiwan-China Relationships Walden C. Rhines CHAIRMAN & CEO Mentor Graphics Corporation U.S.-Taiwan-China Semiconductor Optimization Growing the total
More informationLaker 3 Custom Design Tools
Datasheet Laker 3 Custom Design Tools Laker 3 Custom Design Tools The Laker 3 Custom Design Tools form a unified front-to-back environment for custom circuit design and layout. They deliver a complete
More informationVirtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP
Virtuoso Custom Design Platform GL The Cadence Virtuoso custom design platform is the industry s leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The
More informationImprove Reliability With Accurate Voltage-Aware DRC. Matthew Hogan, Mentor Graphics
Improve Reliability With Accurate Voltage-Aware DRC Matthew Hogan, Mentor Graphics BACKGROUND Consumer expectations for longer device operations at sustained performance levels means designing for reliability
More informationTutorial I: Cadence Innovus ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim
Tutorial I: Cadence Innovus ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim I. Setup for Cadence Innovus 1. Copy the following files into your working
More informationidfm Flow: An ECO Implementation of Metal, Via Filling
idfm Flow: An ECO Implementation of Metal, Via Filling Giriraj Kakol, Dibyendu Goswami, Rajesh Karturi, Suryanarayana Prekke, Intel Corporation, Bangalore, India Motivation As the complexity of designs
More informationStarRC Parasitic Extraction
Datasheet StarRC Parasitic Extraction Overview StarRC is the EDA industry s gold standard for parasitic extraction. A key component of Synopsys Galaxy Design Platform, it provides a siliconaccurate and
More informationANALOG MICROELECTRONICS ( A)
ANALOG MICROELECTRONICS (304-534A) IBM 130 nm CMOS Technology An Introduction to Cadence Virtuoso Layout Tool and the Analog Simulation Environment Prepared By - Azhar A. Chowdhury Updated by Ming Yang
More informationLow k 1 Logic Design using Gridded Design Rules
SPIE Advanced Lithography Conference 2008 6925-68 Tela Innovations, ASML 1 Low k 1 Logic Design using Gridded Design Rules Michael C. Smayling a, Hua-yu Liu b, Lynn Cai b a Tela Innovations, Inc., 655
More informationTaming the Challenges of 20nm Custom/Analog Design
Taming the Challenges of 20nm Custom/Analog Design Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The
More informationAbstract Editor (Last updated: Oct. 23, 2008)
Abstract Editor (Last updated: Oct. 23, 2008) Abstract Editor Tutorial This tutorial has been created to discuss all of the steps needed to create an abstract Library Exchange Format (LEF) file for custom
More informationOCTOSHAPE SDK AND CLIENT LICENSE AGREEMENT (SCLA)
OCTOSHAPE SDK AND CLIENT LICENSE AGREEMENT (SCLA) This is a License Agreement (the "Agreement") for certain code (the Software ) owned by Akamai Technologies, Inc. ( Akamai ) that is useful in connection
More informationPhysical Verification Challenges and Solution for 45nm and Beyond. Haifang Liao Celesda Design Solutions, Inc.
Physical Verification Challenges and Solution for 45nm and Beyond Haifang Liao Celesda Design Solutions, Inc. Nanometer Design Era Semiconductor feature size has been shrunk 500x in 40 years Space for
More informationTopology Router. - The Intelligence of an Engineer. - The Skill of a Designer - The Speed of Auto-Routing. Dave Wiens. Director, Market Development
Topology Router - The Intelligence of an Engineer - The Skill of a Designer - The Speed of Auto-Routing Dave Wiens Director, Market Development Challenges Reduction of design-cycle time for products that
More informationEnhanced Layout Optimization of Sub-45nm Standard, Memory Cells and Its Effects
Enhanced Layout Optimization of Sub-45nm Standard, Memory Cells and Its Effects Seung Weon Paek*, Dae Hyun Jang*, Joo Hyun Park*, Naya Ha*, Byung-Moo Kim*, Hyo Sig Won*, Kyu-Myung Choi*, Kuang-Kuo Lin
More informationSOLVING MANUFACTURING CHALLENGES AND BRINGING SPIN TORQUE MRAM TO THE MAINSTREAM
SEMICON Taipei SOLVING MANUFACTURING CHALLENGES AND BRINGING SPIN TORQUE MRAM TO THE MAINSTREAM Joe O Hare, Marketing Director Sanjeev Aggarwal, Ph.D., VP Manufacturing & Process Everspin Company Highlights
More informationChip/Package/Board Interface Pathway Design and Optimization. Tom Whipple Product Engineering Architect November 2015
Chip/Package/Board Interface Pathway Design and Optimization Tom Whipple Product Engineering Architect November 2015 Chip/package/board interface pathway design and optimization PCB design with Allegro
More informationSOI based platforms for IoT optimized Applications. Director
SOI based platforms for IoT optimized Applications Carlos Mazure Executive Director Director Giorgio Cesana Executive Co- Agenda SOI Consortium in a nut shell IoT opportunities and challenges FD-SOI Solutions
More informationSetting up the IBM 65nm libraries in Cadence 6.1
Setting up the IBM 65nm libraries in Cadence 6.1 Preeti Mulage v1 (Jan, 2010) 1. Setting up Cadence 6.1 and Spectre MMSIM 7.1 a. You need to incorporate these lines in order to bring up the latest 6.1
More informationTutorial II: Cadence Virtuoso ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof.
Tutorial II: Cadence Virtuoso ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim I. Setup for Cadence Virtuoso 1. Copy the following files into your
More informationECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 1: Introduction to VLSI Technology Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Course Objectives
More informationPACKAGE DESIGNERS NEED ASSEMBLY-LEVEL LVS FOR HDAP VERIFICATION TAREK RAMADAN MENTOR, A SIEMENS BUSINESS
PACKAGE DESIGNERS NEED ASSEMBLY-LEVEL LVS FOR HDAP VERIFICATION TAREK RAMADAN MENTOR, A SIEMENS BUSINESS D E S I G N T O S I L I C O N W H I T E P A P E R w w w. m e n t o r. c o m INTRODUCTION Contrary
More informationCommon Platform Ecosystem Enablement
Joe Abler Common Platform Ecosystem Enablement IBM provides a complete Foundry solution Innovative technology Leadership road map with advanced SiGe & RF offerings Leading-edge CMOS process development
More informationSoitec ultra-thin SOI substrates enabling FD-SOI technology. July, 2015
Soitec ultra-thin SOI substrates enabling FD-SOI technology July, 2015 Agenda FD-SOI: Background & Value Proposition C1- Restricted July 8, 2015 2 Today Ultra-mobile & Connected Consumer At Any Time With
More informationUNIVERSITY OF WATERLOO
UNIVERSITY OF WATERLOO UW ASIC DESIGN TEAM: Cadence Tutorial Description: Part I: Layout & DRC of a CMOS inverter. Part II: Extraction & LVS of a CMOS inverter. Part III: Post-Layout Simulation. The Cadence
More informationBest Practices for Implementing ARM Cortex -A12 Processor and Mali TM -T6XX GPUs for Mid-Range Mobile SoCs.
Best Practices for Implementing ARM Cortex -A12 Processor and Mali TM -T6XX GPUs for Mid-Range Mobile SoCs. Cortex-A12: ARM-Cadence collaboration Joint team working on ARM Cortex -A12 irm flow irm content:
More informationManufacturability-Aware Physical Layout Optimizations
Manufacturability-Aware Physical Layout Optimizations David Z. Pan and Martin D. F. Wong Dept. of Electrical and Computer Engineering, Univ. of Texas at Austin Dept. of Electrical and Computer Engineering,
More informationOpenPDK Production Value and Benchmark Results
OpenPDK Production Value and Benchmark Results Philippe MAGARSHACK Executive Vice-President, Design Enablement and Services June 2 nd, 2014 ST s Strong technology portfolio : Several R&D Partnerships &
More informationDRVerify: The Verification of Physical Verification
DRVerify: The Verification of Physical Verification Sage Design Automation, Inc. Santa Clara, California, USA Who checks the checker? DRC (design rule check) is the most fundamental physical verification
More informationUsage Guide of Calibre on DRC check
Usage Guide of Calibre on DRC check Zheng Huan Qun November 2006 The guide shows the flow of DRC check with the tool Calibre of Mentor Graphics. The design kits used in the guide is AMS kits. The method
More informationAN2734 Application note S-Touch design procedure Introduction
Application note S-Touch design procedure Introduction The purpose of this application note is to provide the system/hardware engineers enough ground knowledge to start the design of capacitive touch inferface
More informationStandard Cell Library Evaluation with Multiplelithography-compliant. Synopsys Pin Access Checking Utility
Standard Cell Library Evaluation with Multiplelithography-compliant verification and Improved Synopsys Pin Access Checking Utility Yongfu Li, Wan Chia Ang, Chin Hui Lee, Kok Peng Chua, Yoong Seang Jonathan
More informationBaseband IC Design Kits for Rapid System Realization
Baseband IC Design Kits for Rapid System Realization Lanbing Chen Cadence Design Systems Engineering Director John Rowland Spreadtrum Communications SVP of Hardware Engineering Agenda How to Speed Up IC
More informationSOITEC REPORTS SECOND QUARTER FY 17 REVENUES OF 56.7 M, UP 4% COMPARED WITH THE SECOND QUARTER OF FY 16 AT CONSTANT EXCHANGE RATES
SOITEC REPORTS SECOND QUARTER FY 17 REVENUES OF 56.7 M, UP 4% COMPARED WITH THE SECOND QUARTER OF FY 16 AT CONSTANT EXCHANGE RATES Continued sustainable growth in Communication & Power 200-mm wafer sales
More informationpre- & post-processing f o r p o w e r t r a i n
pre- & post-processing f o r p o w e r t r a i n www.beta-cae.com With its complete solutions for meshing, assembly, contacts definition and boundary conditions setup, ANSA becomes the most efficient and
More informationVirtuoso System Design Platform Unified system-aware platform for IC and package design
Unified system-aware platform for IC and package design The Cadence Virtuoso System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean
More informationChip/Package/Board Design Flow
Chip/Package/Board Design Flow EM Simulation Advances in ADS 2011.10 1 EM Simulation Advances in ADS2011.10 Agilent EEsof Chip/Package/Board Design Flow 2 RF Chip/Package/Board Design Industry Trends Increasing
More informationAvaya Call Management System CMS Upgrade Express (CUE) Customer Requirements
Avaya Call Management System CMS Upgrade Express (CUE) Customer Requirements February 2010 2010 Avaya Inc. All Rights Reserved. Notice While reasonable efforts were made to ensure that the information
More informationAnnouncements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends
EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture : Scaling Trends Announcements No office hour next Monday Extra office hours Tuesday and Thursday -3pm CMOS Scaling Rules Voltage, V / α tox/α
More informationA Method to Implement Layout Versus Schematic Check in Integrated Circuits Design Programs
A Method to Implement Layout Versus Schematic Check in Integrated Circuits Design Programs Radu Gabriel Bozomitu, Daniela Ionescu Telecommunications Department Faculty of Electronics and Telecommunications,
More informationSpecifying the PCB Design Rules and Resolving Violations
Specifying the PCB Design Rules and Resolving Violations Summary This article introduces the PCB Design Rules System, in particular how rules are created and applied to objects in a design. It also describes
More informationDigital VLSI Design. Lecture 9: Routing
Digital VLSI Design Lecture 9: Routing Semester A, 018-19 Lecturer: Dr. Adam Teman January 5, 019 Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources
More informationASIC design flow considering lithography-induced effects
DESIGN FOR MANUFACTURABILITY ASIC design flow considering lithography-induced effects K. Cao and J. Hu Abstract: As VLSI technology scales towards 65 nm and beyond, both timing and power performance of
More informationEE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL)
EE115C Digital Electronic Circuits Tutorial 4: Schematic-driven Layout (Virtuoso XL) This tutorial will demonstrate schematic-driven layout on the example of a 2-input NAND gate. Simple Layout (that won
More informationPushing 193i lithography by Joint optimization of Layout and Lithography
Pushing 193i lithography by Joint optimization of Layout and Lithography Peter De Bisschop Imec, Leuven, Belgium Semicon Europe Messe Dresden, Germany Lithography session October 12, 2011 Semiconductor-Industry
More informationLaboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013
CME 342 (VLSI Circuit Design) Laboratory 6 - Using Encounter for Automatic Place and Route By Mulong Li, 2013 Reference: Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Erik Brunvand Background
More informationChallenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba
Challenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba Advanced Mask Technology Center Dresden, Germany Senior Member of Technical Staff Advanced Mask Technology Center Dresden Key Facts
More informationECE260B CSE241A Winter Tapeout. Website:
ECE260B CSE241A Winter 2007 Tapeout Website: http://vlsicad.ucsd.edu/courses/ece260b-w07 ECE 260B CSE 241A Tapeout 1 Tapeout definition What is the definition of the tapeout? There is no standard definition
More informationSystematic Defect Filtering and Data Analysis Methodology for Design Based Metrology
Systematic Defect Filtering and Data Analysis Methodology for Design Based Metrology Hyunjo Yang* a, Jungchan Kim a, Taehyeong Lee a, Areum Jung a, Gyun Yoo a, Donggyu Yim a, Sungki Park a, Toshiaki Hasebe
More information