Manufacturing Challenges and their Implications on Design

Transcription

1 Manufacturing Challenges and their Implications on Design Phiroze Parakh, Ph.D

2 45nm/32nm Design Challenges MANUFACTURING VARIATIONS PROCESS & DESIGN VARIATIONS LARGE DESIGNS LOW POWER

3 The Evolution of Signoff PRE-TAPE EOUT 130nm 90nm 65nm 45nm DRC DRC DRC DRC Critical Feature Analysis Critical Feature Analysis Critical Area Analysis Litho-friendly Design Critical Feature Analysis Critical Area Analysis Litho-friendly Design Litho-aware Silicon Modeling 32nm

4 Variability vs. Yield, Cause vs. Effect Variability: spread in process/layout parameters and is inherently caused by the litho-process Yield: measure of success-rate in fabrication process Yi ld f il li iti f i bilit Yield-failure: limiting case of variability. The effect of a high-σ event!

5 P&R, RET and Fabrication P&R timing place opt route clock logic RET: Backend GDS2 OPC CAA LFD Corners Gate delays RC/µm Design rules Litho model Mask Layers Parametric Variations Defect densities FAB: Tapeout yield wafer models Design rules

6 How does robust optimization address variability? low V th fast RC Fab & Test Universe Typical optimization centered around nominal process high V th slow RC Robust optimization seeks to cover larger process conditions

7 Taxonomy Parametric (process) y Spatial (wafer/die) Proximity (local position) Systematic Variability Dynamic Temperature/Voltage N.B.T.I Electro-migration Random Particle Defects Implant L.E.R What can be addressed by P&R?

8 Example Systematic Parametric Variation: PV-Bands V23 M3 M2 The bands represent a range of simulations across Dose, Defocus, and Mask-Bias Drawn!= Actual Calibre OlympusLFD

9 Understanding Lithography is the first step Mask Wafer λ NA: sin(θ) Resist Critical_dimension = κ 1 * λ / Numerical_Aperture

10 How is sub-λ possible? λ = 193nm; sin(θ) 1 CD 193nm CD = k 1 * λ/na NA can be > 1 if we use 1.2 immersion lithography η water = NATake advantage of the mask-spectrum Partially coherent imaging κ Off-axis illumination Annular light 0.48 sources 0.44 Improve the mask via OPC κ 1 90nm 65nm 45nm 32nm 22nm 0.24

11 Optics: Initial Source of Variability Mask Resist Wafer 1.1 E E 0 Exposure Latitude Mask Bias Focus σ(cd image ) limits σ(e 0 ) σ(dof) limited by σ(cd image ) σ(cd image ) limits σ(cd mask ) The variance of CD image, Exposure, Masks and Focus are coupled

12 Parametric Variability in Lithography space Fat M1 Variability is a measure of the change in the image over changes in Dose, Focus and Mask-Bias

13 Variability through Timing Corners 250 Inverter driving 25µm of M ps Delay (ps s) Weak: High-Vt Weak: Low-Vt ps C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Corners v, 0 C, best RC 0.9v, 125 C, worst RC Strong: High-Vt Strong: Low-Vt Each corner is a full chip timing tighten the range

14 Robust P&R for DFM place opt route clock logic Timing aware Metal Fill Fast DRC Wire Spreading Double Via Ins. Multi-corner analysis Mentor Olympus DB Litho analysis Litho Errors Advanced Rules CAA / Yield CMP Maps Litho aware CAA LFD OPC CMP

15 Parametric (process) y Spatial (wafer/die) Proximity (local position) Systematic Variability Dynamic Temperature/Voltage N.B.T.I Electro-migration Random Particle Defects Implant L.E.R

16 S Systematic vs. Parametric 80nm 65nm 120nm? 85nm? Actual Shape Can be Simulated Systematic Drawn - Actual Parametric σ(actual) 69nm? 60nm? 64nm? Can we account for Drawn Shapes in Routing?

17 S Metal Pinching (Min-Width) M2 bridge with litho error Pinched (but still ok) PV-band violation OPC: nominal case Rather than make OPC solve for all Process windows, we could make the M2 jog wider

18 S Density based width variation 40nm 20nm variation! 60nm Modeled in RC extraction

19 S Double vias can be a double edged sword 80nm 39nm 43nm Increased contact reliability Decreased metal reliability

20 S Locality!= adjacency Space allows the other side to compensate Symmetry suggests this should be an error M3 min-width idth violation

21 S Robust repair of Litho-Errors Aggressor Zones Expand to fix error Victim Rotate (if possible) Use a fine grid to resolve violation

22 S Systematic vs. Parametric 80nm 65nm 120nm? 85nm? Actual Shape Can be Simulated Systematic Drawn - Actual Parametric σ(actual) 69nm? 60nm? 64nm? Can we account for Drawn Shapes in Timing?

23 S OCV Margins Fudge-factor OCV Margin factor of ~20% This factor masks Location based variation L/Weff variation IR-drop etc.. Robust OCV model each factor

24 S Systematic Density-based Variation for a Timer High density Optical diameter 65nm 45nm 32nm Low density High cell density increased σ(l eff ) Proximity(Density) Based OCV

25 S Parasitic Variation and Chemical Mechanical Polishing Wire thickness (C lateral ) is a function of layer, density and width The dielectric between layers will also vary σ(c substrate ) Per layer CMP variation M3 could be worse than M2! Metal fill makes density consistent Calibre CMP

26 Taxonomy Parametric (process) y Spatial (wafer/die) Proximity (local position) Systematic Variability Dynamic Temperature/Voltage N.B.T.I Electro-migration Particle Defects Random Implant (V th ) L.E.R

27 D Dynamic Variation Time/state dependent Eg: Negative Bias Temp Instability (NBTI) max V th 125 When will we reach max Vth? log(v th h) 25 log(t) Lifetime A comprehensive model of PMOS NBTI degradation, M. Alam. A K map + target t conditions are needed d Also supports delay dependence on IR-drop

28 Taxonomy Parametric (process) y Spatial (wafer/die) Proximity (local position) Systematic Variability Dynamic Temperature/Voltage N.B.T.I Electro-migration Particle Defects Random Implant (V th ) L.E.R

29 R Random variation along timing-path σ(v th ) = K W L Due to variation in number and distribution of dopant atoms in the channel logic_path_depth: v 0.58v clock_path_depth: 2 Different distribution! Same number of atoms σ(logic): σ(v th )* 5 σ(clock): σ(v th )* 2 On clock trees, Random even dopant induced a threshold small voltage difference lowering and fluctuations, in Asen path-depth Asenov. matters.

30 R Random Fault: Critical Area Analysis C.A = P(r) A(r) dr 0

31 R CAA: How is A(r) to be determined? Shorts: PV-Bands 3 possible A(r) Opens: PV-Bands 3 possible A(r) Conservative: Inner band for opens and Outer band for shorts

32 R Improving CAA score C.A = P(r) A(r) dr 0 Tough to spread! Easier Improve A(r) by wire-spreading or wire-sizing

33 R Random Fault: Pattern collapse y M1 mask x y Etch x High aspect ratio, without side support! y x

34 R Pattern collapse Capillary effect θ Young s Modulus used to determine snapping point h s w

35 R Potential For Collapse? Has Support Long Unsupported Imbalanced Too short Well balanced Wire-spreading prevent collapse

36 Conclusion Parametric (process) y Spatial (wafer/die) Proximity (local position) Systematic Variability Dynamic Temperature/Voltage N.B.T.I Electro-migration Random Particle Defects Implant L.E.R Proper models are key to addressing variability

37 Andres Torres Alex Volkov Acknowledgements Shankar Krishnamoorthy

38 Resolution lower-bound Pitch: 21 < 1 λ/na Image The lens is a low pass filter! It will suppress frequencies below CD -1

39 Interference Incident plane wave n*λ θ (n+½)*λ

40 Diffraction Incident plane wave Constructive: n*λ Destructive: (n+½)*λ

41 Sub-λ stressed by need for increased control σ (nm m) Non-uniform wires Vias Uniform wires Variance is larger due to non-uniformity

42 Contacts vs. Metal Is this Double Via needed? Shift the wire & rotate the via? M3 pinch

43 CAA on 45nm design Metal 2 Metal 3 Metal 4 Stripes due to power lines

44 O.C.V: Systematic variation for a Timer σ outside Spherical aberration Focus σ inside Resist Coating, CMP Planarity Etch Thickness σ outside > σ inside Chips inside have less variation they sort into faster bins! Location Based OCV

45 CAA: How is P(r) determined? Inline Particle Detectors shine a laser on the wafer and detect scattered light Scattering intensity is proportional to Scattering intensity is proportional to particle size