Media Instructions, Coprocessors, and Hardware Accelerators. Overview

Transcription

1 Media Instructions, Coprocessors, and Hardware Accelerators Steven P. Smith SoC Design EE382V Fall 2009 EE382 System-on-Chip Design Coprocessors, etc. SPS-1 University of Texas at Austin Overview SoCs offer tremendous potential for targeting applications to particular demands, such as performance, power, cost, etc. How do you take advantage of all those available transistors? Multiple general-purpose processor cores Most Flexible, but typically sub-optimal for specific applications Application-specific instruction set processors (ASIP) MMX media instruction extensions to PCs extend this concept Coprocessors Use well-defined control interface to processor Hardware accelerators Typically custom, memory-mapped interface EE382 System-on-Chip Design Coprocessors, etc. SPS-2 University of Texas at Austin 1

2 Media Instructions: MMX Multimedia applications tend to perform repetitive operations on large quantities of 8 and 16-bit data Filtering Compression Rendering Intel s MMX TM technology is designed to speed-up multimedia and communications applications. The technology includes special instructions and data types that allow such applications to achieve a new level of performance. EE382 System-on-Chip Design Coprocessors, etc. SPS-3 University of Texas at Austin MMX Introduction Processors enabled with MMX technology deliver enough performance to execute compute-intensive communications and multimedia tasks on the standard PC platform. Commonly accelerated applications include graphics, image processing, MPEG video, music synthesis, speech compression, speech recognition, games, video conferencing and more. EE382 System-on-Chip Design Coprocessors, etc. SPS-4 University of Texas at Austin 2

3 Key Attributes of MMX Target Applications Small integer data types Small, highly repetitive loops Frequent multiplies and accumulates Compute-intensive algorithms Highly parallel operations EE382 System-on-Chip Design Coprocessors, etc. SPS-5 University of Texas at Austin MMX Highlights Single Instruction, Multiple Data (SIMD) technique 57 instructions beyond base x86 instruction set Eight 64-bit wide MMX registers Four new data types EE382 System-on-Chip Design Coprocessors, etc. SPS-6 University of Texas at Austin 3

4 MMX SIMD Single Instruction, Multiple Data (SIMD) This allows many pieces of information to be processed with a single instruction, providing parallelism that greatly increases performance. Up to 8-way parallelism EE382 System-on-Chip Design Coprocessors, etc. SPS-7 University of Texas at Austin MMX Data Types Packed Byte: Eight bytes packed into one 64-bit quantity Packed Word: Four 16-bit words packed into one 64-bit quantity Packed Doubleword: Two 32-bit double words packed into one 64-bit quantity Quadword: One 64-bit quantity EE382 System-on-Chip Design Coprocessors, etc. SPS-8 University of Texas at Austin 4

5 MMX Data Types in 64-bit Registers EE382 System-on-Chip Design Coprocessors, etc. SPS-9 University of Texas at Austin MMX Instructions The MMX instructions cover several functional areas: Basic arithmetic operations such as add, subtract, multiply, arithmetic shift and multiply-add Comparison operations Conversion instructions to convert between the new data types - pack data together, and unpack from small to larger data types Logical operations such as AND, AND NOT,OR, and XOR Shift operations Data Transfer (MOV) instructions for MMX register-toregister transfers, or 64-bit and 32-bit load/store operations to memory EE382 System-on-Chip Design Coprocessors, etc. SPS-10 University of Texas at Austin 5

6 MMX Instruction Set Summary EE382 System-on-Chip Design Coprocessors, etc. SPS-11 University of Texas at Austin MMX Instruction Set Summary (2) EE382 System-on-Chip Design Coprocessors, etc. SPS-12 University of Texas at Austin 6

7 PADDW Instruction EE382 System-on-Chip Design Coprocessors, etc. SPS-13 University of Texas at Austin PADDSUW Instruction EE382 System-on-Chip Design Coprocessors, etc. SPS-14 University of Texas at Austin 7

8 PMADDWD Instruction EE382 System-on-Chip Design Coprocessors, etc. SPS-15 University of Texas at Austin PCMPGTW Instruction EE382 System-on-Chip Design Coprocessors, etc. SPS-16 University of Texas at Austin 8

9 PACKSS[DW] Instruction EE382 System-on-Chip Design Coprocessors, etc. SPS-17 University of Texas at Austin MMX Applications Chroma Keying EE382 System-on-Chip Design Coprocessors, etc. SPS-18 University of Texas at Austin 9

10 MMX Applications: Chroma Keying pcmpeqw EE382 System-on-Chip Design Coprocessors, etc. SPS-19 University of Texas at Austin MMX Applications: Chroma Keying pandn EE382 System-on-Chip Design Coprocessors, etc. SPS-20 University of Texas at Austin 10

11 MMX Applications: Vector Dot product EE382 System-on-Chip Design Coprocessors, etc. SPS-21 University of Texas at Austin MMX Applications: Vector Dot product EE382 System-on-Chip Design Coprocessors, etc. SPS-22 University of Texas at Austin 11

12 MMX Applications: Matrix Multiplication EE382 System-on-Chip Design Coprocessors, etc. SPS-23 University of Texas at Austin MMX Applications: Matrix Multiplication Instruction counts EE382 System-on-Chip Design Coprocessors, etc. SPS-24 University of Texas at Austin 12

13 Coprocessors Integrated with processor control logic Tightly-Coupled Coprocessors Task typically completes in a few cycles Small amounts of data Processor stalls waiting for the coprocessor Communication with coprocessor typically via registers and dedicated control signals Coprocessor ports Examples: ARM (ARM7TDMI); Texas Instruments TMS320C55x processors EE382 System-on-Chip Design Coprocessors, etc. SPS-25 University of Texas at Austin Tightly-Coupled Coprocessors Memory System Instruction decode TMS320C55x Register file T C C I/f TCC instructions TCC EE382 System-on-Chip Design Coprocessors, etc. SPS-26 University of Texas at Austin 13

14 Coprocessors Loosely-Coupled Coprocessors Used for larger tasks than is the case for tightly-coupled coprocessors Task runs in parallel with main processor May take many cycles per task Large amounts of data that coprocessor may access independent of main processor Still uses standard coprocessor interface EE382 System-on-Chip Design Coprocessors, etc. SPS-27 University of Texas at Austin Loosely-Coupled Coprocessors chips from AFE Analog Front end (AFE) Input buffer Datapath Address Generation PN Generation Controller & Counters Instruction buffer DSP/ coprocessor interface Output buffer Address Generation SRAM DSP CORRELATOR COPROCESSOR EE382 System-on-Chip Design Coprocessors, etc. SPS-28 University of Texas at Austin 14

15 Hardware Accelerators Similar to loosely-coupled coprocessors, but Ad hoc interface to controlling processor Usually memory-mapped Bus-based, FIFO, or register data interfaces Typically, the processor transfers data to the accelerator, issues a go command, and then collects result data later. Polled or interrupt-based interface Accelerator may have its own path to/from memory Often fixed function EE382 System-on-Chip Design Coprocessors, etc. SPS-29 University of Texas at Austin Common Hardware Accelerator Applications Graphics Compression Audio/Video Decoding Encryption: RSA, DES, AES Router frame queueing, port selection EE382 System-on-Chip Design Coprocessors, etc. SPS-30 University of Texas at Austin 15

16 Hardware Accelerator Interface: Interrupts or Polling? Polling interfaces usually require the processor to read a memory-mapped register to determine the state of the accelerator. Can the accelerator accept new input data? Is the accelerator done with its current task? Has the accelerator generated an error condition? Polling interfaces offer minimal latency between the setting of a condition on the accelerator and its discovery by the controlling processor. But processor isn t doing other work while it polls EE382 System-on-Chip Design Coprocessors, etc. SPS-31 University of Texas at Austin Hardware Accelerator Interface: Interrupts or Polling? Interrupt-based interfaces allow the accelerator to signal conditions to the controlling processor. Interrupt latency is longer than is achievable via the polling method. But the processor can more easily proceed with other work while the accelerator is busy with a task. Interrupts more efficient for coarse grained parallelism (i.e., larger tasks with looser and less frequent synchronization requirements) Interrupts may not work for real-time control tasks with tight schedules EE382 System-on-Chip Design Coprocessors, etc. SPS-32 University of Texas at Austin 16

17 So, When to Use Media Instructions, Coprocessors and Accelerators Media instructions are ideal so long as they meet performance goals. Highly flexible Parallelism from SIMD structures only Coprocessors are preferred when well-defined interfaces are available. Relatively easy to program May or may not stall the processor Accelerators use ad hoc, application-specific interfaces to achieve high levels of performance and parallelism Least flexible EE382 System-on-Chip Design Coprocessors, etc. SPS-33 University of Texas at Austin Conclusions Media instructions, coprocessors, and hardware accelerators each provide a means of increasing system performance. Decision factors for which to use include: Performance requirements Ease of programming Hardware design effort required Flexibility required Nature of parallelism achievable in target application Coarse or fine grained Small scale, localized or broad EE382 System-on-Chip Design Coprocessors, etc. SPS-34 University of Texas at Austin 17