COSC 3215 Embedded Systems Laboratory

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1 COSC 3215 Embedded Systems Laboratory Lab 5 The Altera, Verilog and QuartusII Introduction This lab is an introduction to the Altera FPGA development board and the accompanying FPGA programming environment QuartusII. All software development will be carried out using the digital hardware description language Verilog. You can download a free version QuartusII from the following website -quartus_we.jsp. Note you will have to get a license file prior to using QuartusII on your home computer. Specification Your task is use the laboratory Altera FPGA development board to implement a 4-bit Binary Coded Decimal (BCD) adder. The BCD adder must read the value of the FLEX_SWITCH dipswitch as two hexadecimal numbers with bits 7 through 4 representing one number, and bits 3 through 0 representing the other number, add these two numbers together and display the sum on the two digit 7-segment display. Hints The following predefined symbols are available to help simplify your task: DEC_SEG: Performs the binary to 7-segment decode operation. Reference Reading Altera UP2 Development Kit Users Guide Upds.pdf Introductory Verilog information. Ciletti (2003) Chapter 4, Appendices A-D Other possibilities include introductory digital logic texts such as Brown and Vranesic or Mano and Kine PreLab Determine what a BCDAdder is and implement one in Verilog according to the lab specifications. COSC3215 Lab5 Winter

2 Procedure Make appropriate notes and answer all questions clearly in your lab book. Creating The Project 1. Launch the QuartusII application and create a new project entitled MyBCDAdder using the New Project Wizard using the File menu command. A tutorial on creating new projects is available in the online QuatrusII help section. 2. Directory, Name and Top-Level Entity [page 1 of 6]: Specify the working directory for your project using the browse button. 3. Name your project as MyBCDAdder and name the top level entity in your project as MyBCDAdder. 4. Add Files [page 2 of 6]: There are no files to add but you must specify a user library. Click the User Library Pathnames button and enter the library path c:\altera\quatrus41sp2\libraries\up1coreqii as the library name. Click next to continue. 5. EDA Tool Settings [page 3 of 6]: Ensure all the tool names are specified as <none>. Click next to continue. 6. Device Family [page 4 of 6]: Select the FLEX10K from the list of available device families. Ensure that you have answered yes to Do you want to assign a specific device? Click next to continue. 7. Select a Target Device [page 5 of 6]: Change the speed grade filter to Any and scroll down to the bottom of the list of available devices and select the EPF10K70RC240-4 device. Click Finish to continue. Adding Symbols and Blocks To Your Design 1. Create a new block design file using the File/New menu command. Select the Block Diagram/Schematic File under the Device Design Files tab and click OK. Save this file as MyBCDAdder.bsf. 2. Add the BCDAdder block to your design file by first selecting the Block Tool, located on the toolbar then positioning the cursor to a location within the Block Editor, clicking and holding the left mouse button and drawing a box. Release the left mouse button when you are finished. COSC3215 Lab5 Winter

3 3. Select the Selection and Smart Drawing Tool, located on the toolbar and move the cursor over the block you just created. 4. Click the right mouse button and select the Block Properties option. 5. Rename the block to BCDAdder. 6. Click on the I/Os properties tab and enter all the input output connections to your BCDAdder. Click OK when you are done. 7. Still using the Selection and Smart Drawing Tool move the cursor away from the BCDAdder block and click the right mouse button. 8. Select the Insert/Symbol option. 9. Expand the c:/altera/quartus41sp2/libraries/ list and then further expand the UP1coreQII library. Select the DEC_7SEG symbol and click OK. 10. Drag the DEC_7SEG symbol to the location of your choice within the block editor window and click the left mouse button when you are done. 11. You will need two DEC_7SEG symbols so repeat steps 9 to Repeat steps 8 and 9. Expand the primitives/pin subdirectory in the library list and select the output symbol. Click OK when you are done. 13. Place the output pin somewhere to the right of one of the DEC_7SEG symbols, preferably in alignment with one of the segment outputs. 14. Repeat steps 12 and 13 for each of the segment outputs for both DEC_7SEG symbols. 15. Add one more output pin and place it somewhere above or below the DEC_7SEG symbols. This output pin will be used for simulation purposes. 16. Following the steps described above add two input pins and place these to the left of the BCDAdder block. Connecting Symbols and Blocks 1. Select the Selection and Smart Drawing Tool from the toolbar. 2. Place the cursor on the segment_a output pin of one of the DEC_7SEG symbols and click and hold the left mouse button. COSC3215 Lab5 Winter

4 3. Draw a line/node connection to one of the output pins that you placed to the right of the DEC_7SEG symbol and release the left mouse button. 4. Repeat steps 1 through 3 for each of the segment outputs for both DEC_7SEG symbols. 5. Again still using the Selection and Smart Drawing Tool move the cursor over to one of the input pins and click and hold the left mouse button. 6. Draw a line to an edge of the BCDAdder block and release the left mouse button. 7. Repeat steps 5 and 6 for the second input pin. 8. Place the cursor on the hex_digit[3..0] input pin of one of the DEC_7SEG symbols. 9. Click and hold the let mouse button and draw a line over to the BCDAdder block symbol and release the left mouse button. 10. Place the cursor on the hex_digit[3..0] input pin of the other DEC_7SEG symbol. 11. Click and hold the left mouse button and move the cursor directly over the bus connection running between the BCDAdder and the other DEC_7SEG symbol and release the left mouse button. 12. Move the cursor over to the output connection that is to be used for simulation purposes and draw a bus connection over to the bus connecting the BCDAdder block and the DEC_7Seg symbols. Naming Pins and Connections 1. Using the Smart Selection Design Tool double click the default pin_name for the output pin connected to the segment_a output of the DEC_7SEG symbol that will display the ones digit of the BCDAdder output. 2. Enter Digit1_SegA as the name for this pin. Press Enter when you are done. 3. Name all the output pins in your design following the Digit1_Segx format. 4. Again using the Smart Selection Design Tool double click the default pin_name for one of the input pins in your design. COSC3215 Lab5 Winter

5 5. The input pins, as they are intended in this design do not represent individual connections but multiple connections or busses and as such must be named differently. Type the name for your input pin as follows A[3..0]. The [3..0] specifies the number of signals and the order of significance. 6. Repeat step 5 for the second input pin naming it B[3..0]. 7. Using the Smart Selection Design Tool move the cursor directly over the Digit1 DEC_7SEG hex_digit[3..0] bus connection and click the right mouse button. 8. Select the Properties option and name this bus connection as Y[3..0] under the General properties tab. Click OK when you are done. 9. Using the Smart Selection Design Tool move the cursor directly over the Digit2 DEC_7SEG hex_digit[3..0] bus connection and click the right mouse button. 10. Select the Properties option and name this bus connection as Y[7..4] under the General properties tab. Click OK when you are done. 11. Using the Smart Selection Design Tool move the cursor directly over the bus connection at the BCDAdder block side and click the right mouse button. 12. Select the Properties option and name this bus connection as Y[7..0] under the General properties tab. Click OK when you are done. 13. Using the Smart Selection Design Tool move the cursor over the green <> symbol attached to the Y[7..0] bus connection and double click the left mouse button. 14. Under the General properties tab change the type to output. 15. Select the mappings properties tab and type Y[7..0] for the I/O on block. 16. Move the cursor over to the green <> symbol attached to the conduit connection between the A[3..0] input and the BCDAdder block and double click the left mouse button. 17. Set the type to input then select the Mappings property tab. 18. Select A[3..0] from the I/O on block list box. COSC3215 Lab5 Winter

6 19. Select A[3..0] from the Signals in conduit list box and click Add. Click OK when you are done. 20. Repeat 16 through 19 for the B[3..0] input. 21. Check your schematic file for errors using the Processing/Analyze Current File menu command and remove any errors that you may have. Creating a Verilog Module From a Block Symbol 1. Select the Selection and Smart Drawing Tool from the toolbar and move the cursor somewhere inside the BCDAdder symbol. 2. Click the right mouse button and select the Create Design File from Selected Block option. 3. Select the Verilog HDL file type and click OK. 4. Edit the newly created Verilog file by placing your code for the BCD adder below the // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! comment. 5. Check your Verilog code for errors using the Processing/Analyze Current File menu command and remove any errors that you may have. Building Your Project Now that al the pieces are in place it is time to build your project so you can first simulate the design and then when you are satisfied with the simulation you can program the Altera Development board with your design. 1. Select the Processing/Start Compilation menu command. 2. Investigate and remove any errors you may have. You may be able to ignore some or all the warning messages. Preparing for the Simulation When simulating the functionality of your BCDAdder it is important to know how fast your BCDAdder is, or what is the propagation delay between the input and output of your BCDAdder. The propagation delay can be measured simply by using the timing Analyzer Tool. Using the Timing Analyzer Tool 1. Select the Tools/Timing Analyzer menu command. 2. Click the Start button and wait for the analysis to complete. COSC3215 Lab5 Winter

7 3. Select the tpd properties tab and record the slowest propagation delay time for your design. This value should be taken into consideration when implementing timing signals in your design simulation. Simulating Your BCDAdder 1. Open the Tools/Options menu command and select the Waveform Editor option. 2. Select the Extend file end time to fit all waveforms option in the When Inserting waveforms list of choices. 3. Change the default end time value to a value suitable to simulate all the possible combinations of A and B for your BCDAdder. Click OK when you are done. 4. Add a Vector Waveform File to your project using the File/New menu command. 5. Select the Other Files properties tab in the New dialog box and select the Vector Waveform File and click OK when you are done. 6. The Vector Waveform File should now be open. Move the cursor to the left windowpane of the Vector Waveform File and click the right mouse button. 7. Select the Insert Node or Busses option. 8. Click the Node Finder button. 9. Click the List button in the newly opened Node Finder window. 10. In the Nodes Found list select the A, B and Y nodes and add these to the. Click OK when you are done. 11. Click OK to close the Insert Node or Bus dialog box. 12. Move the cursor over to the windowpane listing the node names and left click on the A node. 13. With the cursor still over the selected node click the right mouse button and select the Value/Count Value option and click OK. 14. Change the radix: to hexadecimal. 15. Repeat steps 12 to 14 for the B input only do not click OK at the end of 14. COSC3215 Lab5 Winter

8 16. Select the Timing properties tab and enter a suitable value for the Count every: value. Click OK. Note you are expected to simulate every possible combination of A and B. 17. Save this file as MyBCDAdder.wvf. 18. Open the Simulator Tool using the Tools/Simulator Tool menu command and click the Start button. 19. When the simulation process is finished click the Report button. 20. A window entitled Simulation Waveforms should open, if not then open the simulator waveforms window. 21. Determine if your BCDAdder is working by examining the displayed waveforms. What is the clock period for the A input? How does this compare to the propagation delay you measured earlier? 22. If you feel that the A input clock period is incorrect for your BCDAdder you can change the period by editing the A input waveform in the MyBCDAdder.vwf file. 23. Open the MyBCDAdder.vwf file. 24. Move the cursor over the windowpane listing the node names and left click on the A node. 25. Select the Value/Count Value option and click OK. 26. Click on the Timing properties tab and enter a suitable value for the Count every: parameter. Leave the units as nanoseconds, ns. Click OK when you are done. 27. Repeat steps 24 through 26 for the B node. Enter the same Count every: value you used for A node and enter 16 for the Multiplied by: parameter. Click Ok when you are done. 28. Simulate your design and determine if your BCDAdder is functioning properly by examining the simulation waveforms. 29. Did the changes you made help? If you are satisfied with the simulation results expand on the critical points and print out the simulation waveforms. COSC3215 Lab5 Winter

9 Assigning Physical Device Pins Now that you have verified your design through the simulation process it is time to load it onto the Altera development board. 1. The first step is to assign physical device pins to all the I/O pins in your design. 2. Open the pin assignment window using the Assignments/Pins menu command. 3. De-select the Show assignments for specific nodes check box in the Node Filter section. 4. Select the Pin option under Locations in the Category section. 5. Double click on the Location column for node A[0] and scroll through the list and select PIN_ Consult the Upds.pdf file and repeat step 5 for all the other nodes in your design. Refer to Table 6. FLEX_SW1 Pin Assignments for the A and B inputs and Table 7.FLEX_DIGIT Segment I/O Connections for the seven-segment display. Programming the Altera Board 1. Consult the Upds.pdf file and verify the JTAG jumper settings are set to configure the FLEX 10K device only according to Table 2. JTAG Jumper Settings. 2. Select the Tools/Programmer menu option. 3. Verify that the Hardware Type is set to ByteBlasterMV(LPT1). 4. Click the Add File button and select the MYBCDAdder.sof file. 5. Check the Program/Configure programming option for the device chain. 6. When the programming cycle completes change the FLEX dipswitch setting and verify the functionality of your BCDAdder. 7. Make any design changes and repeat the simulation/programming part until you are satisfied with its performance. COSC3215 Lab5 Winter

10 Lab Evaluation You must show the.v and.wdf files that you have created and also demonstrate how your waveforms verify the BCD adder to the lab demonstrator (note this means you must show convincing evidence that it works). All code and simulation results should be submitted to the submit directory using the submit command. COSC3215 Lab5 Winter

Contents. Appendix B HDL Entry Tutorial 2 Page 1 of 14

Contents. Appendix B HDL Entry Tutorial 2 Page 1 of 14 Appendix B HDL Entry Tutorial 2 Page 1 of 14 Contents Appendix B HDL Entry Tutorial 2...2 B.1 Getting Started...2 B.1.1 Preparing a Folder for the Project...2 B.1.2 Starting Quartus II...2 B.1.3 Creating