FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT

Transcription

1 FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT DIC1: Schematic Design Entry, Simulation & Verification DIC2: Schematic Driven Layout Drawing (SDL) Design Rule Check (DRC) Layout Versus Schematic (LVS) - Parasitic Extraction (PEX)

2 LAB GUIDE DIGITAL INTEGRATED CIRCUIT DIC1: Schematic Design Entry, Simulation & Verification Create project folder Before creating a design, you must create a folder storing all the design files. From the desktop, right click on the mouse and open a terminal window. At the command shell, make a project directory Type: mkdir project Then click ENTER. Invoking the Pyxis Design Manager To invoke the tsmc130nm technology design kit Type. /EDA/TSMC_013_TDK/source.bash To invoke the Pyxis design manager Type dmgr_ic You will see the Project Design Manager as in the figure below. This project navigator will manage all your circuit design. 2

3 Create project folder Opening Existing Project Click on File > Open, then load the directory path to /EDA/TSMC_013_TDK/ic_projects/Pyxis_SPT and click OK The Pyxis_SPT project will be displayed at the explorer pane with its library. Creating New Project To create new project click on File > New > Project and at the technology library path, point to /EDA/TSMC_013_TDK/tech_libs/generic13 Then, name your project in the Project path, for example /newhome/shome/username/project/tutorial. Then click OK. *please key in your own username You should see the tutorial project will be displayed at the explorer pane. Next, you need to add the Pyxis Libraries. On the Manage External/Logic Libraries, click on Add Standard Libraries to add libraries as shown in the screenshot below. Include some external libraries by browsing the path to /EDA/TSMC_013_TDK/external_libs/GenericAnalog /EDA/TSMC_013_TDK/external_libs/GenericGates /EDA/TSMC_013_TDK/logic_libs/mgc_libs Then click OK to add the the libraries to your project. Copying Libraries To copy the libraries from the Pyxis_SPT to your current project, click on Pyxis_SPT project at the explorer pane. On the view pane, select the library named GenericPLL and MixedSims, then right click and select Copy. Click on your project named tutorial, then right click and select Paste Special, a Copy Object window will pop up. Check the Follow References option and click OK. The copied file will be displayed under the tutorial project. Then, close the Pyxis_SPT project by clicking on the project name and then right click and choose Close Hierarchy. 3

4 Pyxis Schematic Design Setup and Create a schematic Sheet Select your project name at the Project Navigator, click on the New Library icon under menubar: and name your library name as component and click OK. Select the component library you have created before under your project and make sure it is highlighted, and then click on New Schematic icon under the menubar. New Schematic window will pop out and at Cell name column type your cell name as inverter. Then click OK The Pyxis Design Manager will automatically invoke the Pyxis Schematic. To draw a schematic (a) Insert components On the Pyxis Schematic, from the menubar click on Add > Instance.. or use hotkey I, then point the browser by scrolling down at Object section to $GENERIC13/symbols and select nmos and click on OK. Then paste the nmos on the schematic sheet. Then, highlight the component and use the hotkey Q to change the width of the nmos to 1u and click OK. To add PMOS transistor you can use hotkey I to call the instance and use hotkey Q to change the symbol path under the attribute section. The width of the pmos remains as default and then click OK. Components you need in creating an inverter are: 4

5 o nmos, pmos, VDD, Ground, PortIn and PortOut Refer to the following schematic to insert desired components. To obtain the VDD, Ground, PortIn and PortOut, click on Add > Instance and replace the library path under Look in tab by scrolling down at the Object section to mgc_libs> generic_lib and then select the needed component. (b)add wires Click on Add > Wire or you may use shortkey key W and connect all the components to create the inverter circuit. To add a wire between 2 points, click once on the starting point, move the cursor to the other point, and double click. To exit from this adding wire function, press Esc. (c) Name ports/nets Unselect all first (by pressing F2 ), then to name the PortIn and PortOut, to in and out, highlight the component and then use the hotkey Q to edit the property of the instance. The Edit Object window will pop out and then change the Net Name in the Value column respectively. When done, click OK. Check Schematic After the schematic is captured, you need to check the schematic to make sure there are no errors on it. At the menubar, click on File > Check Schematic. Check to see if the process passed or failed. Notice that at the bottom of the window, it reads inverter/schematic/sheet1 passed check If schematic check failed, fix the schematic accordingly by referring the Transcript area window. Otherwise, the log window can be closed. This can be 5

6 done by clicking on the middle mouse button and dragging it towards the left and let go. To save the schematic, click on File > Save Sheet > Default. Generate Symbol Next is to generate a symbol to represent the design. Click on Add > Generate Symbol from the menu bar. At the Generate Symbol window, you may change the symbol by clicking on Choose Shape.. For inverter, you may select Buffer as the shape and click OK. The symbol generated will be seen. To check the symbol, click on File > Check Symbol at the menubar. Check to make sure the symbol passed check at the bottom of the window. Save the symbol by clicking File > Save Symbol > Default. Notice that once you have saved the symbol, one of the pins of the symbol will be highlighted. Close the symbol window. Hold on to the middle mouse button, drag it to the left and let go. Simulation Creating a testbench What you need to do next is to create a testbench graphically. This testbench is used to create stimulus to simulate your inverter. Click on component library on the Project Navigator window. Make sure it is highlighted. Click on the New Schematic icon under menubar, a window will pop up. In the cell name column, name your schematic as inverter_tb. This is to create another schematic file with the name inverter_tb. Then, click OK. The Pyxis Schematic window pops up. The first thing you need to do is to instantiate your inverter design in the testbench. Click on Add > Instance..>Choose Symbol at the menubar, a file browser will pop up. Browse to $TUTORIAL/component and click on the Component library and select the inverter which is the inverter symbol that you have designed earlier. Click on OK. Move your cursor to place the instance in the schematic sheet. Components you need to add to the test bench are: VDD, Ground, pulse_v_source and dc_v_source, After placing the inverter, click on Add > Instance..> Choose Symbol or with the hotkey I to call the components form the library. Click on mgc_libs > generic_lib > ground to select Ground and paste it on the schematic. To add the VDD component by using the same library, use hotkey I and press Q. Then, change the library path to obtain the required component and paste it on the schematic. 6

7 To obtain the pulse_v_source and dc_v_source browse, click Add > Instance and browse to mgc_libs > sources_lib and select the component respectively. Then, paste it on the schematic. Refer to the following to insert the components and to connect the wires, click on Add > Wire or you may use the shortcut key W. To modify the DC source, select the pulse_v_source and it will be highlighted. Then, press Q to change its property. When the Edit Objects window pops up, change the data to the following: delay: 1ns initial_value: 0V period: 50ns pulse_value: 1.2V t_fall: 1ns t_rise: 1ns width: 20ns Click OK when done. To name the nets (in, out), Select the wire and right click and select Name Net. Key in the net name (in or out) in the Property Value column at the bottom of the window. After creating the testbench, you now need to check the schematic of the testbench to make sure it is correct. To check schematic, click on File > Check Schematic from the menubar. Once passed, save the schematic by clicking on File > Save Sheet >Default. Simulation mode To reopen your testbench schematic, you can select and double clicks the testbench schematic on the Pyxis Design Manager. 7

8 Click on Simulation on the Schematic Edit palette to enter to the simulation mode. A Entering Simulation Mode window will pops up, click OK to continue. At toolbar on your left, click on Setup Simulator/Viewer > Setup Netlister. A Setup Spice Netlister window pops up and at the Set Node 0 column, type GROUND. This tells the netlister that any node with the name GROUND is the ground. Then, at the Output type section, select EldoSPICE. Click OK when done. Click on Setup Libraries.. on the toolbar to setup the simulation. A Setup Simulation window pops up as shown in the figure below. On the Libraries, select Typical in the Active model scenario. Click on Analysis Setup on the same window and check the Transient as the analysis methods, then click on Apply. Expand the Analysis Setup and select the Transient Setup. Key in the Output Start Time with the value of 0 and click on Apply. On the same window, click on Edit Waveforms. Select Voltage on the Type section and click on Add Wave Output icon on the right toolbar to probe all the nodes at the end of the simulation as shown in the figure below. 8

9 Repeat the previous step to add Current to probe currents in the simulation. After setting the probes, you are now ready to run simulation. Go back to the testbench schematic and click on the Run Simulator icon on the toolbar. Make sure if your simulation is successfully done. Notice that at the bottom of the window, it reads Simulation completed successfully. If your simulation fails, end your simulation by clicking End Sim and do the corrections on your schematic, before repeating the whole simulation process again. View simulation result Once the simulation process is completed, click on more > View Wave > New Window at the toolbar to view the simulation waveforms. Click on the TRAN folder to view all the waveforms. 9

10 LAB GUIDE DIGITAL INTEGRATED CIRCUIT DIC2: Circuit Layout, DRC, LVS, PEX Create Schematic Driven Layout (SDL) Since the inverter schematic has been drawn in the first lab, we are going to create an SDL (Schematic Driven Layout). Firstly, select your inverter folder on the Pyxis Design Manager. Make sure it is highlighted. Then click on the New Layout icon under the menubar to create a new layout sheet. In the Layout Name column, name your layout with any name e.g inverter_layout and click OK to continue. Pyxis layout will be invoked automatically with all files setting is retrieved from the TSMC013 design kit. Specify the component to be imported on the Component column as $TUTORIAL/component/inverter Specify the Cell name as $TUTORIAL/component/inverter/inverter_layout Specify the Process as $GENERIC13/process/generic13 Specify the Rules as $GENERIC13/process/sdl_process_rules Click on OK to confirm Pyxis layout will automatically create a SDL with both schematic and layout sheet is display at the same time. Layout design Select the pmos on the schematic sheet, make sure it is highlighted and click on Inst on DLA Logic Palette on your right. The pmos layout will be automatically generated, then paste it on the layout sheet. To unselect a highlighted device, press F2. Repeat the same procedure to generate the nmos layout and place it on the sheet. To align the 2 transistor, you may use hotkey V. Zoom in to see clearly by press and hold the middle mouse button and draw: You can see yellow lines connecting the devices. They are called overflows. These are the connections (using metal or poly layer) you need to make. Next, unselected a highlighted device by pressing F2, then select the PortIn on the schematic and click on Port on the DLA Logic. The PortIn will be generated and paste it on the bottom left corner of the pmos device. *If the PortIn is showing in Poly layer (red layer), press 4 to change the Poly layer to Metal1 layer (blue layer). Repeat the step to generate the PortOut and paste it on the bottom right of the pmos. Do the same thing to VDD and Ground and place it on the top left corner of the pmos and bottom left corner of the nmos respectively.

11 Use hotkey V to align the ports and make sure it is Metal1 layer. The layout will look as the screenshot below. VDD PortIn PortOut Ground To expand the VDD port to the right, press hotkey E and click on the right edge of the VDD port and drag it to the right. *you can use hotkey V to align it with pmos. To expand vertically upward, press hotkey E and click on the top edge of the VDD port and drag upward. Repeat the same step to expand the Ground port. Next, select the VDD port and click Easy Edit > Via > Fill Selected on the IC Palette as shown below. Choose m1nwell on the ICdevice ShapeVia window, and click OK to add nwell contact on the PMOS device. 11

12 Repeat the same step to add pwell contact to the nmos device (GROUND port) by selecting mp1psub on the Icdevice Shape Via window. To get a better view of the whole layout, you can zoom out the view. This can be done by holding the middle mouse button and make a short stroke movement to upper right. The devices generated by SDL are instances. This means the device is not flat. Try to peek inside the devices by using the peekdown stroke. Hold the middle mouse button and make this stroke. The contacts (white squares) inside the nmos/pmos becomes visible. You won t be able to edit the nmos/pmos because it is an instance generated based on the schematic. To unpeek, hold on the middle mouse button and make this stroke. The following figure shows a screen shot of what you suppose to get when you peek into the nmos and pmos. Nwell Contact Pwell Contact Layout Routing The following figure shows the connections of the inverter layout that you supposed to draw. 12

13 Poly Contact Poly layer Metal1 layer The source of the pmos is tied to VDD while nmos goes to GND. To route the source terminal of the pmos to VDD port, use hotkey I. Make sure the layer is Metal1 layer. Press 4 for metal select. Click at source of the nmos device and move the Metal1 layer upward to the VDD port and use hotkey W to change the width of the Metal1 layer to 0.26 or Shift+W to automatically change the Metal1 witdh as same with width of the source of the pmos. Minimum Metal1 with is Next route the source terminal of the nmos device to the ground and connect the output drain terminal of the pmos and nmos together. To route the poly of the pmos to the poly of the nmos. Use the hotkey I and press 3 to change the Metal1 layer back to Poly layer and connect both poly gates together. Repeat previous step to route the output port to the drain of the two transistors, but press 4 to change to Metal1 layer back. Drag the Metal1 layer to the right and double click on the output port. To add the Poly Contact, use the hotkey I and press 3 to change to Poly layer, then route Poly of 2 transistors to the input port and at the same time press 4 to add Metal1 with Via connection to connect Poly with Metal1 layer on top of input port as shown in the figure below 13

14 To label the ports, select the MET1TEXT layer on the Layer Palette and click Add Text.. icon on the left toolbar. Press hotkey Q to change the Value column as in. You can adjust the size of the Text Height column e.g 0.3. Then click apply and paste it to the input port. *Make sure that the names are same as the ones you named in your schematic. Repeat the same step to add text value out, VDD and Ground respectively. Press ESC key to terminate commands that are still active. Design Rule Check (DRC) From the menu bar, select Tools > Calibre > Run DRC. To invoke the Calibrate nmdrc. Click on Run DRC to start the DRC checking. RVE (Result Viewing Environment) window shows DRC errors. On the Calibre RVE window, click on down arrow to find the errors in the report. If there are errors, click on the error to see the details. Double click on the coordinate to locate the error in layout window. You can automatically zoom in the DRC error. At the Calibre DRC RVE window, select Setup > Options from the main menu. Click on Zoom cell view to highlights by:. Enter a number (e.g. 0.7). This is the zoom ratio. Click OK to close. Double click on an error to see the zoom in. Fix all the DRC errors accordingly. After editing, save the cell and rerun the DRC. This is done by going back to the Calibre DRC and click on Run DRC again. When prompted to Overwrite Layout File, click OK. Close the RVE and Calibre DRC windows. Layout Versus Schematic (LVS) We will now proceed to LVS. We will be comparing the netlist from the schematic and the netlist from the layout 14

15 In Pyxis layout, invoke Calibre nmlvs by selecting Tool > Calibre > Run LVS from the menu bar. Click on the Setup on menubar of nmlvs window to enable the LVS option. Click on LVS Option and key in VDD and GROUND at the Power nets and Ground nets column to define the power and ground net of the layout. Click on Run LVS. Once completed, the LVS Report will display the LVS results. Take a look at the LVS Report. If you see a big X, it means there are errors. The RVE window is useful to debug the layout. Click on an error, an explanation will appear at the bottom pane. To debug, right click near the error and select Highlight Net. The Pyxis layout will highlight the respective net. Try fixing all the errors and rerun the LVS by simply click on Run LVS. After modifying the layout, remember to run DRC again. Make sure your layout is DRC and LVS clean. Close the LVS Report and Calibre windows. Parasitic extraction Parasitic extraction is after DRC and LVS checking. The purpose of parasitic extraction is to extract the parasitics (R & C) from the circuit layout. Make sure that your layout is DRC and LVS clean. Click on Tools > Calibre > Run PEX and PEX screen pops up Click on the Inputs tab. Select Netlist tab and check the Export from schematic viewer option. Change the Top Cell of the netlist to inverter, and then click OK. Click on Outputs tab and under Netlist tab, select DSPF as the format instead of ELDO. Click on Setup and enable PEX options 15

16 Select LVS Option tab and key in VDD as the Power nets and GROUND as the Ground nets. Click on Run PEX. This will start RC extraction. A new netlist with parasitic will be generated e.g inverter_layout.pex.netlist Re-simulate the design with the parasitic data. Open the inverter_tb > eldonet on the Pyxis Design Manager to invoke the Pyxis Schematic to enter to the simulation mode of the testbench directly Select the INVERTER1 instant symbol and click on Tools > Parasitics > Add DSPF to include the parasitic netlist for simulation. Browse the previously generated parasitics netlist in the Choose DSPF column to $PROJECT/component/inverter/inverter_layout.cal/inverter_layout.pex.net list and select on DSPF in the Simulate using devices from: option and click OK. The parasitic netlist will be displayed on the schematic once the parasitic netlist is included. Click on Run Simulator on the toolbar to re-simulate the design with the parasitic data. Once the simulation process is completed, click on more > View Wave > New Window on the toolbar to view the simulation waveforms. You can compare with the original simulation waveform with the output waveform with parasitic. 16