Alternative controller FSM implementation approaches based on:

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1 Overview lternative controller FSM implementation approaches based on: classical Moore and Mealy machines jump counters microprogramming (ROM) based approaches branch sequencers horizontal microcode vertical microcode lternative Ways to Implement Processor FSMs "Random " based on Moore and Mealy esign Classical Finite State Machine esign ivide and Conquer pproach: Time-State Method Partition FSM into multiple communicating FSMs Exploit MSI Functionality: Counters, Multiplexers, ecoders Microprogramming: ROM-based methods irect encoding of next states and outputs CS 5 - Spring - Controller Implementation - CS 5 - Spring - Controller Implementation - Random Perhaps poor choice of terms for "classical" FSMs Contrast with structured logic: PL/PL, P, ROM Could just as easily construct Moore and Mealy machines with these components Moore Machine State iagram L L L Note capture of MBR in these states IR MR MR Mem,,, Mem MBR MBR C = = ST ST RES IF IF IF IF3 O IR MR, C MBR MR Mem,,, MBR Mem = PC PC MR, PC + PC MR Mem,,, Mem MBR MBR IR = IR MR BR = MR Mem, BR,, Mem MBR MBR + C C = IR PC CS 5 - Spring - Controller Implementation - 3 CS 5 - Spring - Controller Implementation - 4 Memory-Register Interface Timing IF IF IF IF IF3 Moore Machine iagram Clock IR<5> IR<4> C<5> Next State State 6 states, 4 bit state register Next State : 9 Inputs, 4 Outputs Output : 4 Inputs, 8 Outputs WIT Mem Bus Latch MBR Invalid ata Latched Invalid ata Latched Valid ata Latched Valid data latched on IF to IF3 transition because data must be valid before can go low ata Valid Output PC PC + PC PC BUS IR BUS BUS MR BUS PC MR Memory ddress Bus Memory ata Bus MBR MBR Memory ata Bus MBR MBUS MBUS IR MBUS LU B MBUS C RBUS C RBUS MBR These can be implemented via ROM or PL/PL Next State: 5 x 4 bit ROM Output: 6 x 8 bit ROM CS 5 - Spring - Controller Implementation - 5 CS 5 - Spring - Controller Implementation - 6

2 Moore Machine State Table Moore Machine State Table IR<5> IR<4> C<5>Current State Next State Register Transfer Ops X X X X X RES () X X X X RES () IF () PC X X X X IF () IF () PC MR, PC + PC X X X IF () IF () X X X IF () IF () X X X IF () IF () MR Mem, Read, X X X IF () IF3 (), Mem MBR X X X IF3 () IF3 () MBR IR X X X IF3 ()O () X X O () L () X X O () ST () X X O () () X X O () BR () CS 5 - Spring - Controller Implementation - 7 IR<5> IR<4> C<5>Current State Next State Register Transfer Ops X X X X L () L () IR MR X X X L () L () MR Mem, Read, X X X L () L (), Mem MBR X X X X L () IF () MBR C X X X X ST () ST () IR MR, C MBR X X X ST () ST () MR Mem, Write, X X X ST () IF (), MBR Mem X X X X () () IR MR X X X () () MR Mem, Read, X X X () (), Mem MBR X X X X () IF () MBR + C C X X X BR () IF () X X X BR () BR () X X X X BR () IF () IR PC CS 5 - Spring - Controller Implementation - 8 Moore Machine State Transition Table Observations: Extensive use of on't Cares Inputs used only in a small number of state e.g., C<5> examined only in BR state IR<5:4> examined only in O state Some outputs always asserted in a group ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step CS 5 - Spring - Controller Implementation - 9 Moore Machine Implementation ssume PL/PL implementation style First idea: run ESPRESSO with naive state assignment product terms Compare with 5 product terms in ROM implementation!.i 9.i 9.o 4.o 4.ilb reset wait ir5 ir4 ac5 q3 q q q.ilb reset wait ir5 ir4 ac5 q3 q q q.ob p3 p p p.ob p3 p p p.p 6.p e e CS 5 - Spring - Controller Implementation - Moore Machine Implementation NOV assignment does better NOV State ssignment SUMMRY onehot_products = best_products = 8 best_size = 44 states[]:if Best code: states[]:if Best code: states[]:if Best code: states[3]:if3 Best code: states[4]:o Best code: states[5]:l Best code: states[6]:l Best code: states[7]:l Best code: states[8]:st Best code: states[9]:st Best code: states[]: Best code: states[]: Best code: states[]: Best code: states[3]:br Best code: states[4]:br Best code: states[5]:res Best code: CS 5 - Spring - Controller Implementation - 8 product terms improves on! Synchronous Mealy Machines Standard Mealy Machine has asynchronous outputs These change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges One approach: non-overlapping clocks Synchronizer Synchronizer Circuitry Circuitryat at Inputs Inputsand and Outputs Outputs ' ' Q Q Output STTE STTE STTE Output CS 5 - Spring - Controller Implementation - ' Q ' Q Output

3 Synchronous Mealy Machines Synchronous Mealy Machine Case I: Synchronizers at Inputs and Outputs Case II: Synchronizers on Inputs cycle cycle cycle S / cycle cycle cycle S / S ' S ' S S '/ S ' asserted in Cycle, becomes asserted after cycle delay! This is clearly overkill! CS 5 - Spring - Controller Implementation - 3 asserted in Cycle, follows in next cycle Same as using delayed signal (') in Cycle! CS 5 - Spring - Controller Implementation - 4 Synchronous Mealy Machines Case III: Synchronized Outputs cycle cycle cycle S / S ' asserted during Cycle, ' asserted in next cycle Effect of delayed one cycle CS 5 - Spring - Controller Implementation - 5 Synchronous Mealy Machines Implications for Processor FSM lready erived Consider inputs:,, IR<5:4>, C<5> Latter two already come from registers, and are sync'd to clock Possible to load IR with new instruction in one state & perform multiway branch on opcode in next state Best solution for and : synchronized inputs» Place flipflops between these external signals and the» control inputs to the processor FSM» Sync'd versions of and delayed by one clock cycle CS 5 - Spring - Controller Implementation - 6 Time State ivide and Conquer Overview Classical pproach: Monolithic Implementations lternative "ivide & Conquer" pproach:» ecompose FSM into several simpler communicating FSMs» Time state FSM (e.g., IFetch, ecode, Execute)» Instruction state FSM (e.g., L, ST,, BRN)» Condition state FSM (e.g., C <, C ) CS 5 - Spring - Controller Implementation - 7 Time State (ivide & Conquer) Time State FSM Most instructions follow same basic sequence iffer only in detailed execution sequence Time State FSM can be parameterized by opcode and C states Instruction State: stored in IR<5:4> Condition State: stored in C<5> = = IR = = L ST BRN C<5>= C T T T T3 T4 T5 T6 C < T7 C<5>= CS 5 - Spring - Controller Implementation - 8 BRN C / (L + ST + ) BRN + (ST )/ (L + )

4 Time State (ivide & Conquer) Jump Counter eneration of Microoperations PC: PC + PC: T PC MR: T MR Memory ddress Bus: T + T6 (L + ST + ) Memory ata Bus MBR: T + T6 (L + ) MBR Memory ata Bus: T6 ST MBR IR: T4 MBR C: T7 L C MBR: T5 ST C + MBR C: T7 IR<3:> MR: T5 (L + ST + ) IR<3:> PC: T6 BRN : T + T6 (L + ) : T6 ST : T + T6 (L + ST + ) Concept Implement FSM using MSI functionality: counters, mux, decoders Pure jump counter: only one of four possible next states CLR N LO N+ XX HOL Single "Jump State" function of the current state Hybrid jump counter: Multiple "Jump States" function of current state + inputs CS 5 - Spring - Controller Implementation - 9 CS 5 - Spring - Controller Implementation - Pure Jump Counter Problem with Pure Jump Counter Inputs Count, Load, Clear Clear Load Count CLOCK Jump State Synchronous Counter State Register NOTE: No inputs to jump state logic ifficult to implement multi-way branches O Extra States: L ST BR al State iagram 4 O 5 8 O BR 6 9 O 7 L ST blocks implemented via discrete logic, PLs/PLs, ROMs Pure Jump Counter State iagram CS 5 - Spring - Controller Implementation - CS 5 - Spring - Controller Implementation - RES Hybrid Jump Counter Implementation Example IF Inputs Count, Load, Clear Clear Load Count CLOCK Jump State Synchronous Counter State Register Load inputs are function of state and FSM inputs State assignment attempts to take advantage of sequential states 5 L L 6 IF IF 3 O 4 ST 8 ST 9 BR 3 L 7 CS 5 - Spring - Controller Implementation - 3 CS 5 - Spring - Controller Implementation - 4

5 Implementation Example, Continued = (s + s5 + s8 + s) + (s + s3) + (s + s6 + s9 + s) = (s + s3) + (s + s6 + s9 + s) CLR = + s7 + s + s3 + (s9 ) CLR = s7 s s3 (s9 + ) L = s4 Contents of Jump State ROM ddress Contents (Symbolic State) (L) (ST) () (BR) CS 5 - Spring - Controller Implementation - 5 /S9 Implementation Example, continued Cnt PL /S S Implement /S9 S9 using active lo /S6 S6 5 7 HOL PL /S3 S /S S /S S P T 3 5 RCO 8 Jump State Q 8 9 IR5 IR<5> 5 C QC C 7 8 IR<4> 4 B QB 3 B 6 7 IR4 3 Q /S4 LO 3 4 / CLR 3 /S7 OR N /S /S3 / / NOTE: ctive lo Implement CLR outputs from CS 5 - Spring - Controller Implementation - 6 decoder /S5 /S4 /S3 /S /S /S /S9 /S8 /S7 /S6 /S5 /S4 /S3 /S /S /S Jump Counter CLR,, L implemented via Mux CLR = CLRm + CLR = CLRm + ctive Lo outputs: hi input inverted at the output Note that is active hi on counter so invert MUX inputs! /CLRm / IR5 IR4 /CLR Jump State 3 IR<5> IR<4> / / /L /CLR P T 63 RCO Q C QC B QB Q LO CLR S3 S S S S3 S S S S3 S S S E4 E4 E4 + + E E E E E E E E E E9 / E9 E9 EOUT EOUT EOUT E7 E7 /CLRm E7 E4 E4 + E4 E E E / E E E E E E CS 5 - Spring - Controller Implementation - 7 C B \S3 \S \S \S \S9 \S8 \S7 \S6 \S5 \S4 \S3 \S \S \S /L Microoperation implementation PC = PC + PC = S PC MR = S MR Memory ddress Bus = (S + S + S5 + S6 + S8 + S9 + S + S) Memory ata Bus MBR = (S + S6 + S) MBR Memory ata Bus = (S8 + S9) MBR IR = S3 MBR C = S7 C MBR = IR5 IR4 S4 C + MBR C = S IR<3:> MR = (IR5 IR4 + IR5 IR4 + IR5 IR4) S4 IR<3:> PC = C5 S3 = (S + S + S5 + S6 + S + S) = (S8 + S9) = (S + S + S5 + S6 + S8 + S9 + S + S) :, CLR, L function of current state + Why not store these as outputs of the Jump State ROM? Make and Current State part of ROM address 3 x as many words, 7 bits wide CS 5 - Spring - Controller Implementation - 8 Branch Sequencers Branch Sequencers Concept Implement Next State via ROM ddress ROM with current state and inputs Problem: ROM doubles in size for each additional input Note: Jump counter trades off ROM size vs. external logic Only jump states kept in ROM Even in hybrid approach, state + input subset form ROM address I n p u t s 4 Way Branch Sequencer Mux Mux β α a a a a3 a4 a5 x x x x 64 Word ROM Z Y X W C S o i n g t n r o l a l s N α β α β α β α β W X Y Z Branch Sequencer: between the extremes Next State stored in ROM Each state limited to small number of next states lways a power of Observe: only a small set of inputs are examined in any state CS 5 - Spring - Controller Implementation - 9 state Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states CS 5 - Spring - Controller Implementation - 3

6 Branch Sequencer Example Processor FSM Processor CPU esign Example S3 S S S s<3> s<> s<> s<> S3 S S S 5 5 E4 E4 C<5> C<5> E E E E E E E9 E9 EOUT E7 EOUT \a E7 IR<5> E4 IR<4> E4 E E E E + E + E lpha, Beta multiplexer input setup CS 5 - Spring - Controller Implementation - 3 \ b ROM RESS ROM CONTENTS (, Current State, a, b) Next State Register Transfer Operations RES X X (IF) PC MR, PC + PC IF (IF) (IF) MR Mem, Read, IF (IF) MR Mem, Read, (IF) Mem MBR IF (IF) (O) MBR IR O (L) IR MR (ST) IR MR, C MBR () IR MR (BR) IR MR CS 5 - Spring - Controller Implementation - 3 Example Processor FSM Branch Sequencers ROM RESS ROM CONTENTS (, Current State, a, b) Next State Register Transfer Operations L X X (L) MR Mem, Read, L (L) Mem MBR (L) MR Mem, Read, L X X (RES) MBR C ST X X (ST) MR Mem, Write,, MBR Mem ST (RES) (ST) MR Mem, Write,, MBR Mem X X () MR Mem, Read, () () MR Mem, Read, X X (RES) MBR + C C BR (RES) (RES) IR PC CS 5 - Spring - Controller Implementation - 33 lternative Horizontal Implementation I N P U T S a and b MUX Control M U M X U X a b ab ab 3 n bit state register 3 4: MUX bit atapath Control Signals Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be :! dding length to ROM word saves on bits vs. doubling words Vertical format: (4 + 4) x 64 = 5 ROM bits Horizontal format: (4 + 4x4 + ) x6 = 5ROMbits CS 5 - Spring - Controller Implementation - 34 ab ab n- n- n- n- bit n : MUX bit Microprogramming Microprogramming How to organize the control signals Implement control signals by storing 's and 's in a ROM Horizontal vs. vertical microprogramming Horizontal: ROM output for each control signal Vertical: encoded control signals in ROM, decoded externally some mutually exclusive signals can be combined helps reduce ROM length Register Transfer/Microoperations 4 Register Transfer operations become Microoperations: PC BUS BUS MR IR BUS ata Bus MBR MBR BUS RBUS MBR RBUS C MBR MBUS C LU PC MBUS LU B PC + PC BUS PC LU PSS B MR ddress Bus MBR ata Bus C RBUS BUS IR LU Result RBUS CS 5 - Spring - Controller Implementation - 35 CS 5 - Spring - Controller Implementation - 36

7 Horizontal Microprogramming Horizontal Microprogramming a mux b mux Horizontal Branch Sequencer, Mux bits 4 x 4 Next State bits Control operation bits 4 bits total Next States 3 PC BUS IR BUS MBR BUS RBUS C C LU MBUS LU B LU PSS B MR ddress Bus MBR ata Bus BUS IR BUS MR ata Bus MBR RBUS MBR MBR MBUS CS 5 - Spring - Controller Implementation - 37 PC PC + PC BUS PC C RBUS LU Result RBUS Moore Processor ROM Current State (ddress) RES () IF () IF () IF () IF3 () O () L () L () L () ST () ST () () () () BR () BR () a mux b mux Next States 3 lpha inputs: =, = IR<5> Beta inputs: = C<5>, = IR<4> PC BUS IR BUS MBR BUS RBUS C C LU MBUS LU B LU PSS B MR ddress Bus MBR ata Bus BUS IR BUS MR ata Bus MBR RBUS MBR MBR MBUS PC PC + PC BUS PC C RBUS LU Result RBUS CS 5 - Spring - Controller Implementation - 38 Horizontal Microprogramming dvantages: most flexibility -- complete parallel access to datapath control points isadvantages: very long control words -- + bits for real processors NOTE: Not all microoperation combinations make sense! Output Encodings: roup mutually exclusive signals Use external logic to decode Example: PC, PC + PC, BUS PC mutually exclusive Save ROM bit with external :4 ecoder CS 5 - Spring - Controller Implementation - 39 Horizontal Microprogramming Partially Encoded Control Outputs LU PSS B MR ddress Bus MBR ata Bus BUS MR C RBUS MBR O N C RBUS T RBUS C R C LU O MBUS LU B L MBR MBUS LU Result RBUS R MBR BUS O BUS IR M PC :4 PC + PC EC BUS PC PC BUS :4 IR BUS EC ata Bus MBR CS 5 - Spring - Controller Implementation - 4 More extensive encoding to reduce ROM word length Typically use multiple microword formats: Horizontal microcode -- next state + control bits in same word Separate formats for control outputs and "branch jumps" may require several microwords in a sequence to implement same function as single horizontal word In the extreme, very much like assembly language programming CS 5 - Spring - Controller Implementation - 4 Branch Jump Compare indicated signal to or Register Transfer Source, estination, Operation ROM Bits Branch Jump Format Condition Select Type Condition Compare 6 Next ddress = = C<5> = IR<5> = IR<4> Register Transfer Format Source estination Operation : NO OP : NO OP : PC BUS : RBUS C : IR BUS : MBUS IR : MBR MBUS : BUS MR : MR M : M MBR : C RBUS : RBUS MBR : LU Res RBUS : BUS PC : MBR M CS 5 - Spring - Controller Implementation - 4 : NO OP : : LU PSS B : PC : PC + PC : Read : Write

8 ROM RESS SYMBOLIC CONTENTS BINRY CONTENTS RES RT PC MR, PC + PC IF RT MR M, Read BJ =, IF IF RT MR M, M MBR, Read BJ =, IF IF RT MBR IR BJ =, IF RT IR MR O BJ IR<5>=, O BJ IR<4>=, ST L RT MR M, Read L RT MR M, M MBR, Read BJ =, L L RT MBR C BJ =, RES BJ =, RES CS 5 - Spring - Controller Implementation - 43 ROM RESS SYMBOLIC CONTENTS BINRY CONTENTS ST RT C MBR RT MR M, MBR M, Write ST RT MR M, MBR M, Write BJ =, RES BJ =, ST O BJ IR<4>=, BR RT MR M, Read RT MR M, M MBR, Read BJ =, RT C + MBR C BJ =, RES BJ =, RES BR BJ C<5>=, RES RT IR PC BJ C<5>=, RES 3 words x ROM bits = 3 bits total versus 6 x 38 = 68 bits horizontal CS 5 - Spring - Controller Implementation - 44 Vertical Programming Controller Block iagram ROM ddress T SRC ST OP LU PSS B 3:8 3 EC 4 PC + PC 5 Read 6 Write Enb 7 RBUS C BUS IR BUS MR 3:8 3 M MBR EC 4 RBUS MBR 5 6 BUS PC Enb 7 MBR M PC BUS IR BUS 3:8 3 MBR BUS EC 4 MR M 5 C RBUS 6 LU Res RBUS Enb 7 PC Condition Condition Selector C<5> IR<5> IR<4> 4: MUX Condition Comparator Microinstruction Type Microinstruction Type L C<5> IR<5> IR<4> Cond L CLR mpc Clk CS 5 - Spring - Controller Implementation - 45 CS 5 - Spring - Controller Implementation - 46 Writeable Control Store Part of control store addresses map into RM» llows assembly language programmer to implement own instructions» Extend "native" instruction set with application specific instructions» Requires considerable sophistication to write microcode» Not a popular approach with today's processors Make the native instruction set simple and fast Write "higher level" functions as assembly language sequences Controller Implementation Summary Control Unit Organization Register transfer operation Classical Moore and Mealy machines Time State pproach Jump Counter Branch Sequencers Horizontal and CS 5 - Spring - Controller Implementation - 47 CS 5 - Spring - Controller Implementation - 48