Alternative Ways to Implement Processor FSMs. Outline. Moore Machine State Diagram. Random Logic. Moore Machine Diagram

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1 Outline lternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time state: ivide and Counter Jump counters Microprogramming (ROM) based approaches» branch sequencers» horizontal microcode» vertical microcode lternative Ways to Implement Processor FSMs "Random " based on Moore and Mealy esign Classical Finite State Machine esign ivide and Conquer pproach: Time-State Method Partition FSM into multiple communicating FSMs Exploit MSI Functionality: Counters, Multiplexers, ecoders Microprogramming: ROM-based methods irect encoding of next states and outputs CS 5 - Spring 24 Lec #2: Control Implementation - CS 5 - Spring 24 Lec #2: Control Implementation - 2 Random Perhaps poor choice of terms for "classical" FSMs Contrast with structured logic: PL/PL, FP, ROM Could just as easily construct Moore and Mealy machines with these components Moore Machine State iagram L L L2 Note capture of MBR in these states IR MR MR Mem, Read/Write, Request, Mem MBR MBR C = = ST ST RES IF IF IF2 IF O IR MR, C MBR MR Mem, Read/Write, Request, MBR Mem = 2 PC PC MR, PC + PC MR Mem, Read/Write, Request, Mem MBR MBR IR = IR MR MR Mem, Read/Write, Request, Mem MBR MBR + C C BR = BR = IR PC CS 5 - Spring 24 Lec #2: Control Implementation - CS 5 - Spring 24 Lec #2: Control Implementation - 4 Memory-Register Interface Timing IF IF2 IF2 IF2 IF Moore Machine iagram Clock IR<5> IR<4> C<5> Next State State 6 states, 4 bit state register Next State : 9 Inputs, 4 s : 4 Inputs, 8 s WIT Mem Bus Latch MBR Invalid ata Invalid ata Valid ata Valid data latched on IF2 to IF transition because data must be valid before can go low ata Valid Read/Write Request PC PC + PC PC BUS IR BUS BUS MR BUS PC MR Memory ddress Bus Memory ata Bus MBR MBR Memory ata Bus MBR MBUS MBUS IR MBUS LU B MBUS C RBUS C RBUS MBR LU These can be implemented via ROM or PL/PL Next State: 52 x 4 bit ROM : 6 x 8 bit ROM CS 5 - Spring 24 Lec #2: Control Implementation - 5 CS 5 - Spring 24 Lec #2: Control Implementation - 6

2 Moore Machine State Table Moore Machine State Table IR<5> IR<4> C<5>Current State Next State Register Transfer Ops X X X X X RES () X X X X RES () IF () PC X X X X IF () IF () PC MR, PC + PC X X X IF () IF () X X X IF () IF2 () X X X IF2 () IF2 () MR Mem, Read, X X X IF2 () IF () Request, Mem MBR X X X IF () IF () MBR IR X X X IF ()O () X X O () L () X X O () ST () X X O () () X X O () BR () CS 5 - Spring 24 Lec #2: Control Implementation - 7 IR<5> IR<4> C<5>Current State Next State Register Transfer Ops X X X X L () L () IR MR X X X L () L () MR Mem, Read, X X X L () L2 () Request, Mem MBR X X X X L2 () IF () MBR C X X X X ST () ST () IR MR, C MBR X X X ST () ST () MR Mem, Write, X X X ST () IF () Request, MBR Mem X X X X () () IR MR X X X () () MR Mem, Read, X X X () 2 () Request, Mem MBR X X X X 2 () IF () MBR + C C X X X BR () IF () X X X BR () BR () X X X X BR () IF () IR PC CS 5 - Spring 24 Lec #2: Control Implementation - 8 Moore Machine State Transition Table Observations: Extensive use of on't Cares Inputs used only in a small number of state e.g., C<5> examined only in BR state IR<5:4> examined only in O state Some outputs always asserted in a group ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step CS 5 - Spring 24 Lec #2: Control Implementation - 9 Moore Machine Implementation ssume PL/PL implementation style First idea: run ESPRESSO with naive state assignment 2 product terms Compare with 52 product terms in ROM implementation!.i 9.i 9.o 4.o 4.ilb reset wait ir5 ir4 ac5 q q2 q q.ilb reset wait ir5 ir4 ac5 q q2 q q.ob p p2 p p.ob p p2 p p.p 26.p e e CS 5 - Spring 24 Lec #2: Control Implementation - Moore Machine Implementation NOV assignment does better NOV State ssignment SUMMRY onehot_products = 22 best_products = 8 best_size = 44 states[]:if Best code: states[]:if Best code: states[2]:if2 Best code: states[]:if Best code: states[4]:o Best code: states[5]:l Best code: states[6]:l Best code: states[7]:l2 Best code: states[8]:st Best code: states[9]:st Best code: states[]: Best code: states[]: Best code: states[2]:2 Best code: states[]:br Best code: states[4]:br Best code: states[5]:res Best code: CS 5 - Spring 24 Lec #2: Control Implementation - 8 product terms improves on 2! Standard Mealy Machine has asynchronous outputs These change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges One approach: non-overlapping clocks Synchronizer Circuitry at Inputs and s ' ' STTE STTE STTE CS 5 - Spring 24 Lec #2: Control Implementation - 2 ' '

3 Synchronous Mealy Machine Case I: Synchronizers at Inputs and s Case II: Synchronizers on Inputs cycle cycle cycle 2 S / cycle cycle cycle 2 S / S ' S ' S S '/ S2 ' asserted in Cycle, becomes asserted after 2 cycle delay! This is clearly overkill! CS 5 - Spring 24 Lec #2: Control Implementation - asserted in Cycle, follows in next cycle Same as using delayed signal (') in Cycle! CS 5 - Spring 24 Lec #2: Control Implementation - 4 Case III: Synchronized s cycle cycle cycle 2 S / S ' asserted during Cycle, ' asserted in next cycle Effect of delayed one cycle CS 5 - Spring 24 Lec #2: Control Implementation - 5 Implications for Processor FSM lready erived Consider inputs:,, IR<5:4>, C<5> Latter two already come from registers, and are sync'd to clock Possible to load IR with new instruction in one state & perform multiway branch on opcode in next state Best solution for and : synchronized inputs» Place flipflops between these external signals and the» control inputs to the processor FSM» Sync'd versions of and delayed by one clock cycle CS 5 - Spring 24 Lec #2: Control Implementation - 6 Time State ivide and Conquer Overview Classical pproach: Monolithic Implementations lternative "ivide & Conquer" pproach:» ecompose FSM into several simpler communicating FSMs» Time state FSM (e.g., IFetch, ecode, Execute)» Instruction state FSM (e.g., L, ST,, BRN)» Condition state FSM (e.g., C <, C ) CS 5 - Spring 24 Lec #2: Control Implementation - 7 Time State (ivide & Conquer) Time State FSM Most instructions follow same basic sequence iffer only in detailed execution sequence Time State FSM can be parameterized by opcode and C states Instruction State: stored in IR<5:4> Condition State: stored in C<5> = = IR = = L ST BRN C<5>= C T T T2 T T4 T5 T6 C < T7 C<5>= CS 5 - Spring 24 Lec #2: Control Implementation - 8 BRN C / (L + ST + ) BRN + (ST )/ (L + )

4 Time State (ivide & Conquer) Jump Counter eneration of Microoperations PC: PC + PC: T PC MR: T MR Memory ddress Bus: T2 + T6 (L + ST + ) Memory ata Bus MBR: T2 + T6 (L + ) MBR Memory ata Bus: T6 ST MBR IR: T4 MBR C: T7 L C MBR: T5 ST C + MBR C: T7 IR<:> MR: T5 (L + ST + ) IR<:> PC: T6 BRN Read/Write: T2 + T6 (L + ) Read/Write: T6 ST Request: T2 + T6 (L + ST + ) Concept Implement FSM using MSI functionality: counters, mux, decoders Pure jump counter: only one of four possible next states N LO N+ XX HOL Single "" function of the current state Hybrid jump counter: Multiple "s" function of current state + inputs CS 5 - Spring 24 Lec #2: Control Implementation - 9 CS 5 - Spring 24 Lec #2: Control Implementation - 2 Pure Jump Counter Problem with Pure Jump Counter Inputs Count, Load, Clear Clear Load Count CLOCK Synchronous Counter State Register NOTE: No inputs to jump state logic ifficult to implement multi-way branches O Extra States: L ST BR al State iagram 4 O 5 8 O BR 6 9 O2 7 L ST blocks implemented via discrete logic, PLs/PLs, ROMs Pure Jump Counter State iagram CS 5 - Spring 24 Lec #2: Control Implementation - 2 CS 5 - Spring 24 Lec #2: Control Implementation - 22 RES Hybrid Jump Counter Implementation Example IF Inputs Count, Load, Clear Clear Load Count CLOCK Synchronous Counter State Register Load inputs are function of state and FSM inputs State assignment attempts to take advantage of sequential states 5 L L 6 IF 2 IF2 O 4 ST 8 ST 9 BR L CS 5 - Spring 24 Lec #2: Control Implementation - 2 CS 5 - Spring 24 Lec #2: Control Implementation - 24

5 Implementation Example, Continued = (s + s5 + s8 + s) + (s + s) + (s2 + s6 + s9 + s) = (s + s) + (s2 + s6 + s9 + s) = + s7 + s2 + s + (s9 ) = s7 s2 s (s9 + ) L = s4 Contents of ROM ddress Contents (Symbolic State) (L) (ST) () (BR) CS 5 - Spring 24 Lec #2: Control Implementation - 25 /S9 Implementation Example, continued Cnt PL /S S Implement /S9 S9 using active lo /S6 S6 5 7 HOL PL /S S /S2 S2 5 7 /S S P T RCO IR5 IR<5> 2 5 C C 2 2 C 7 8 IR<4> 4 B B 22 B 6 7 IR /S4 LO / 4 2 /S7 2 OR N /S2 /S / / NOTE: ctive lo Implement outputs from CS 5 - Spring 24 Lec #2: Control Implementation - 26 decoder /S5 /S4 /S /S2 /S /S /S9 /S8 /S7 /S6 /S5 /S4 /S /S2 /S /S Jump Counter,, L implemented via Mux = m + = m + ctive Lo outputs: hi input inverted at the output Note that is active hi on counter so invert MUX inputs! /m / / IR5 IR<5> 2 IR4 IR<4> / / /L / P T 6 RCO C C B B LO S S2 S S S S2 S S S S2 S S E E E E E E E9 / E9 E9 EOUT EOUT EOUT E7 E7 /m E7 + / E E E E E E CS 5 - Spring 24 Lec #2: Control Implementation C B /L \S \S2 \S \S \S9 \S8 \S7 \S6 \S5 \S4 \S \S2 \S \S Microoperation implementation PC = PC + PC = S PC MR = S MR Memory ddress Bus = (S + S2 + S5 + S6 + S8 + S9 + S + S2) Memory ata Bus MBR = (S2 + S6 + S) MBR Memory ata Bus = (S8 + S9) MBR IR = S MBR C = S7 C MBR = IR5 IR4 S4 C + MBR C = S2 IR<:> MR = (IR5 IR4 + IR5 IR4 + IR5 IR4) S4 IR<:> PC = C5 S Read/Write = (S + S2 + S5 + S6 + S + S2) Read/Write = (S8 + S9) Request = (S + S2 + S5 + S6 + S8 + S9 + S + S2) :,, L function of current state + Why not store these as outputs of the ROM? Make and Current State part of ROM address 2 x as many words, 7 bits wide CS 5 - Spring 24 Lec #2: Control Implementation - 28 Controller Implementation Summary Control Unit Organization Register transfer operation Classical Moore and Mealy machines Time State pproach Jump Counter Next Time:» Branch Sequencers» Horizontal and Vertical Microprogramming CS 5 - Spring 24 Lec #2: Control Implementation - 29