Speed Sign Detection Using Convolutional Neural Network Accelerator IP User Guide
|
|
- Alberta McCormick
- 5 years ago
- Views:
Transcription
1 Speed Sign Detection Using Convolutional Neural Network Accelerator IP FPGA-RD May 2018
2 Contents Acronyms in This Document... 3 Introduction... 4 Reference Design Overview... 5 Block diagram... 5 CNN Accelerator Engine... 6 SD Card Loader... 7 AXI Salve and DDR3 Memory Interface... 8 CSI2 to DVI Interface... 9 Video Processing Module Related Documentation Soft IP Document Diamond Document Hardware Requirements References Technical Support Assistance Revision History Figures Figure 1.1. Embedded Vision Development Kit... 4 Figure 2.1. Speed Sign Detection Reference Design Block Diagram... 5 Figure 3.1. CNN Accelerator IP Core Generation GUI... 6 Figure 4.1. Neural Network Compiler Tool Output File Generation Flow... 7 Figure 7.1. Speed Sign Detection Design *.yml File Snippet FPGA-RD
3 Acronyms in This Document A list of acronyms used in this document. Acronym Definition AXI CNN DRAM DVI FPGA GUI passp PIP SD Card SPI Advanced extensible Interface Convolutional Neural Network Dynamic Random Access Memory Digital Visual Interface Field Programmable Gate Array Graphic User Interface Programmable Application Specific Standard Product Picture In Picture Secure Digital (Memory) Card Serial Peripheral Interface FPGA-RD
4 Introduction This document describes the Speed Sign Detection machine learning neural network reference design. This reference design can be implemented on Lattice s Embedded Vision Development Kit, featuring the Lattice CrossLink passp and ECP5 FPGA. Lattice s Embedded Vision Development Kit Stackable Modular Video Interface Platform (VIP) CrossLink Input Bridge Board LIF-MD6000 passp Two Sony IMX 214 Cameras 2:1 CSI-2 MUX ECP5 Processor Board ECP5-85FGPA Image Signal Processing Sensor Interface IONOS ISP Pipeline All-inclusive demo system with video sources Prototyping header Easy programming via USB interface HDMI Output Bridge Board SiI1136 HDMI assp Non-HDCP Output Figure 1.1. Embedded Vision Development Kit 4 FPGA-RD
5 Reference Design Overview Block diagram Figure 2.1 shows the block diagram of the Speed Sign Detection reference design. ECP5 External DRAM DDR3 Control (ddr3_ip_inst) AXI Slave (axi2lattic e128) CNN Accelerator Engine (lsc_ml_wrap) External Micro SD Card SD Loader (Sd_spi) Frame Data (32x32, 90x90) Result External Camera CSI2_to_DVI_top Video Processing (crop_downscale) External HDMI TX Lattice IP (clarity) Face Tracking Demo Support Design Modules External Components Figure 2.1. Speed Sign Detection Reference Design Block Diagram The Reference Design uses ECP5-85 FPGA containing the following major blocks: CNN accelerator engine SD card to SPI interface AXI Salve interface DDR3 memory interface CSI2 to DVI interface Video processing module FPGA-RD
6 CNN Accelerator Engine Lattice Semiconductor CNN Accelerator IP Core can be used through the Diamond Clarity IP Designer. Engine configuration parameters can be set using the Clarity Designer s IP core configuration GUI, as shown in Figure 3.1. Figure 3.1. CNN Accelerator IP Core Generation GUI For detailed information about Lattice Semiconductor CNN Accelerator IP core, such as input data format, output data format and command format, refer to CNN Accelerator IP Core (FPGA-IPUG-02037). For the command generation by Lattice Neural Network Compiler, refer to Lattice Neural Network Compiler Software (FPGA- UG-02052). 6 FPGA-RD
7 TensorFlow Coffe Speed Sign Detection Using Convolutional Neural Network Accelerator IP SD Card Loader SD card interface in this design is used to get the command data into the DRAM for execution by the CNN accelerator IP. The SD card contains a file that is generated by Lattice Neural Network Compiler Tool. Lattice Neural Network Compiler Tool allows analyzing and compiling a trained neural network, such as what is generated by Caffe or TensorFlow tool, to use with selected Lattice Semiconductor FPGA products. Lattice Neural Network Compiler tool outputs three files: A hardware configuration file (*.yml) that contains information on fixed point converted network and memory allocation. A firmware file (*.lscml) in ASCII format that contains weights coming from a trained model file. Firmware file (*.lscml) must be converted to binary format before loading into the SD card. A firmware file (*.bin) in binary format that can be directly loaded into the SD card. For detailed operation instructions, refer to Lattice Neural Network Compiler Software (FPGA-UG-02052). Figure 4.1 shows the output file generation flow of the Neural Network Compiler Tool. *.proto *.coffemodel SampleImage.jpeg Trained Model HW Configuration Generator *.yml *.pb SampleImage.jpeg *.lscml Firmware (ASCII) Hardware Simulation *.bin Firmware (Binary) Figure 4.1. Neural Network Compiler Tool Output File Generation Flow FPGA-RD
8 AXI Salve and DDR3 Memory Interface AXI interface allows command code to be written in DRAM before execution of CNN Accelerator IP Core. Input data may also be written in DRAM. CNN Accelerator IP Core reads command code from DRAM and performs calculations using internal sub-execution engines. Intermediate data may also be transferred from/to DRAM per command code. 8 FPGA-RD
9 CSI2 to DVI Interface This module implements a bridge function that converts the camera input MIPI CSI data to DVI output using Lattice CrossLink passp and SiI1136 HDMI transmitter. FPGA-RD
10 Video Processing Module The crop_downscale module provides all the necessary functions needed to manage the process of inputting data, receiving output, data and generating a composite image for output to the HDMI interface. Four examples are included in the design: crop_downscale.v crops input to crop_downscale_key.v crops input to crop_downscale_sign.v crops input to crop_downscale_keyl.v crops input to The Speed Sign Detection demo uses crop_downscale_sign.v. Key functions of the code include: Capturing a downscaled image from the camera input module and saving it to a frame buffer. Writing the frame buffer data into CNN accelerator engine during the blanking period. Buffering the output after completion of the image data processing. Creating a Picture In Picture (PIP) bounding box with green borders, and outputting the composite image. Output from CSI2_to_DVI_top module is a stream of data that reflects the camera image. Input image is then downscaled to pixels, stored in a frame buffer and passed to output. Image data is written from the frame buffer into the CNN acceleration engine prior to the start of the processing. Data is then formatted for compatibility with the trained network. The *.yml file provides majority of the information needed for understanding how the input data should be prepared. A snippet of the code in *.yml file for Speed Sign Detection design is shown in Figure 7.1. Figure 7.1. Speed Sign Detection Design *.yml File Snippet 10 FPGA-RD
11 Input Size: [1, 3, 128, 128] indicates one input array consisting of 3 layers of dimensions memblks: 3 total number of memory blocks needed depth_per_mem: 1 number of memory blocks allocated to each memory layer frac: 8 number of bits that is allocated to the fractional component. It is equal to the minimum number of bits to represent this number minus 1. In this case, 3 bits to represent 8-1=7. num_ebr: 16 number of memory blocks. Note despite the variable name, this does not tie directly to the number of Embedded Block Ram (EBR) used in the design. ebr_blk_size: this defines the size of the memory blocks in bytes. Note the blocks have a width of 16 bits and the depth is variable. CNN accelerator engine s ports for results, o_we and o_dout[15:0], can be used to output any number of results. Designer can add a read command to allow reading any data based on the neural network design. In Speed Sign Detection design, the speedsign_post.v accepts the 16-bit output data from CNN accelerator engine, and generates the confidence level for the pre-trained Speed Limit Signs. The results then will be overplayed onto the left side of the output image stream in the magnification bar chart format. FPGA-RD
12 Related Documentation Soft IP Document CNN Accelerator IP Core (FPGA-IPUG-02037) Diamond Document For more information on Lattice Diamond Software, visit Lattice website at: 12 FPGA-RD
13 Hardware Requirements Lattice Embedded Vision Development Kit (LF-EVDK1-EVN) Mini-USB Cable (included in the Lattice Embedded Vision Development Kit) 12 V Power Supply (included with the Kit) HDMI Cable HDMI Monitor (1080p60) Micro-SD Card Adapter (MICROSD-ADP-ENV) Micro-SD Card. Standard Micro-SD card only. FPGA-RD
14 References For more information on FPGA device, visit For complete information on Lattice Diamond Project-Based Environment, Design Flow, Implementation Flow and Tasks, as well as on the Simulation Flow, see the Lattice Diamond. 14 FPGA-RD
15 Technical Support Assistance Submit a technical support case through FPGA-RD
16 Revision History Revision 1.0, May 2018 First release. 16 FPGA-RD
17 7 th Floor, 111 SW 5 th Avenue Portland, OR 97204, USA T
Speed Sign Detection Using Convolutional Neural Network Accelerator IP Reference Design
Speed Sign Detection Using Convolutional Neural Network Accelerator IP FPGA-RD-02035 Version 1.1 September 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Overview... 5 2.1. Block
More informationFace Tracking Using Convolutional Neural Network Accelerator IP Reference Design
Face Tracking Using Convolutional Neural Network Accelerator IP FPGA-RD-02037-1.0 May 2018 Contents 1. Introduction... 4 2. Related Documentation... 5 2.1. Soft IP Document... 5 2.2. Diamond Document...
More informationObject Counting Using Convolutional Neural Network Accelerator IP Reference Design
Object Counting Using Convolutional Neural Network Accelerator IP FPGA-RD-02036 Version 1.1 September 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Related Documentation... 5 2.1.
More informationEVDK Based Speed Sign Detection Demonstration User Guide
EVDK Based Speed Sign Detection Demonstration FPGA-UG-02049 Version 1.1 September 2018 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Functional Description... 6 3. Demo Setup... 8 3.1.
More information2:1 HDMI Switch Demo User Guide
FPGA-UG-02036-A October 2017 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Functional Description... 5 2.1. Overview... 5 2.2. SiI1127A... 5 2.3. SiI1136... 5 2.4. ECP5 Mico32 Design...
More informationLattice Embedded Vision Development Kit User Guide
FPGA-UG-0215 Version 1.3 November 2018 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Functional Description... 6 2.1. CrossLink... 6 2.2. ECP5... 7 2.3. SiI1136... 7 3. Demo Requirements...
More informationMachine Learning Demo User s Guide
Machine Learning Demo User s Guide This document describes the available Machine Learning demos from Lattice. These demos operate on Lattice s Embedded Vision Development Kit, featuring the Lattice CrossLink
More informationEmbedded Vision Solutions
FLEXIBLE SOLUTIONS FOR EMBEDDED VISION PROCESSING AT THE EDGE Embedded Vision Solutions Embedded vision offers a promising future with many exciting new applications entering the market. These systems
More informationMDP Based Face Detection Demonstration User Guide
FPGA-UG-02047 Version 1.0 May 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Functional Description... 4 3. Demo Setup... 5 4. Programming the Face Detection Demo... 7 5. Running
More informationKey Phrase Detection Using Compact CNN Accelerator IP Reference Design
Key Phrase Detection Using Compact CNN Accelerator IP FPGA-RD-02033 Version 1.2 October 2018 Contents 1. Introduction... 3 2. Related Documentation... 3 3. Software Requirements... 3 4. Hardware Requirements...
More informationMDP Based Key Phrase Detection Demonstration User Guide
MDP Based Key Phrase Detection Demonstration FPGA-UG-02048 Version 1.1 September 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Functional Description... 4 3. MDP Board Setup... 5
More informationice40 UltraPlus Display Frame Buffer User Guide
FPGA-UG-02009 Version 1.1 March 2017 Contents 1. Introduction... 3 1.1. Clock Generator Module... 3 1.2. Main Control Module... 3 1.3. SPRAM Module... 4 1.4. Decompress Module... 4 1.5. 8BIT2RGB Module...
More informationProgramming External SPI Flash through JTAG for ECP5/ECP5-5G Technical Note
Programming External SPI Flash through JTAG for ECP5/ECP5-5G FPGA-TN-02050 Version 1.0 October 2017 Contents Acronyms in This Document... 4 1. Introduction... 5 1.1. Features... 5 2. Programming External
More informationice40 UltraPlus Image Sensor Elliptical Crypto Engine (ECC) Demo - Radiant Software User Guide
ice40 UltraPlus Image Sensor Elliptical Crypto Engine (ECC) Demo - Radiant Software FPGA-UG-02060 Version 1.0 June 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Functional Description...
More informationMIPI D-PHY Bandwidth Matrix Table User Guide
FPGA-UG-02041 Version 1.1 May 2018 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Video Format... 6 2.1. Video Resolution and Pixel Clock... 7 2.2. Color Depth... 8 3. MIPI CSI-2/DSI Interfaces...
More informationNEW USE CASES HIGHLIGHT CROSSLINK S BROAD APPLICABILITY
NEW USE CASES HIGHLIGHT CROSSLINK S BROAD APPLICABILITY February 2017 Lattice Semiconductor 111 5 th Ave., Suite 700 Portland, Oregon 97204 USA Telephone: (503) 268-8000 www.latticesemi.com WP0009 Introduction
More informationAccelerating Implementation of Low Power Artificial Intelligence at the Edge
Accelerating Implementation of Low Power Artificial Intelligence at the Edge A Lattice Semiconductor White Paper November 2018 The emergence of smart factories, cities, homes and mobile are driving shifts
More informationMIPI D-PHY Bandwidth Matrix and Implementation Technical Note
MIPI D-PHY Bandwidth Matrix and Implementation FPGA-TN-02090 Version 1.1 January 2019 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Video Format... 6 2.1. Video Resolution and Pixel Clock...
More informationice40 SPRAM Usage Guide Technical Note
TN1314 Version 1.0 June 2016 Contents 1. Introduction... 3 2. Single Port RAM s... 3 2.1. User SB_SPRAM256KA... 3 2.2. SPRAM Port Definitions and GUI Options... 4 3. Power Save States for SPRAM... 6 3.1.
More informationDG0849 Demo Guide PolarFire Dual Camera Video Kit
DG0849 Demo Guide Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Email:
More informationNeural Network Compiler BNN Scripts User Guide
FPGA-UG-02055 Version 1.0 May 2018 Contents 1. Introduction... 3 2. Software Requirements... 3 3. Directory Structure... 3 4. Installation Guide... 4 4.1. Installing Dependencies... 4 4.2. Installing Packages...
More informationLCMXO3LF-9400C SED/SEC Demo
FPGA-UG-02023 Version 1.0 June 2017 Contents 1. Introduction... 4 1.1. Demo Design Overview... 4 1.2. MachXO3-9400 Development Board and Resources... 5 2. Functional Description... 6 3. Demo Package...
More informationByte-to-Pixel Converter IP User Guide
FPGA-IPUG-02027 Version 1.0 July 2017 Contents 1. Introduction... 4 1.1. Quick Facts... 4 1.2. Features... 5 1.3. Conventions... 5 1.3.1. Nomenclature... 5 1.3.2. Data Ordering and Data Types... 5 1.3.3.
More informationCrossLink Hardware Checklist Technical Note
FPGA-TN-02013 Version 1.1 August 2017 Contents Acronyms in This Document... 3 Introduction... 4 Power Supplies... 5 CrossLink MIPI D-PHY and PLL Power Supplies... 5 Power Estimation... 6 Configuration
More informationVIDEO BRIDGING SOLUTION PROMISES NEW LEVEL OF DESIGN FLEXIBILITY AND INNOVATION
VIDEO BRIDGING SOLUTION PROMISES NEW LEVEL OF DESIGN FLEXIBILITY AND INNOVATION May 2016 Lattice Semiconductor 111 5 th Ave., Suite 700 Portland, Oregon 97204 USA Telephone: (503) 268-8000 www.latticesemi.com
More informationThe Path to Embedded Vision & AI using a Low Power Vision DSP. Yair Siegel, Director of Segment Marketing Hotchips August 2016
The Path to Embedded Vision & AI using a Low Power Vision DSP Yair Siegel, Director of Segment Marketing Hotchips August 2016 Presentation Outline Introduction The Need for Embedded Vision & AI Vision
More informationMIPI D-PHY to CMOS Interface Bridge Soft IP
Supporting MIPI CSI-2 and MIPI DSI for Image Sensors and Displays FPGA-IPUG-02004 Version 1.3 January 2017 Contents 1. Introduction... 4 1.1. Quick Facts... 5 1.2. Features... 5 1.3. Conventions... 5 1.3.1.
More informationLow-Cost Serial RapidIO to TI 6482 Digital Signal Processor Interoperability with LatticeECP3
October 2010 Introduction Technical Note TN1214 The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect
More informationUG0850 User Guide PolarFire FPGA Video Solution
UG0850 User Guide PolarFire FPGA Video Solution Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136
More informationice40 UltraPlus RGB LED Controller with BLE User Guide
FPGA-UG-02010 Version 1.1 March 2017 Contents 1. Introduction... 3 2. Demo Setup... 4 2.1. Block Diagram... 4 2.2. Requirements... 5 2.3. Jumper Settings... 5 3. Programming the Bitmaps to the MDP Board...
More informationECP5 Product Families Update - Errata to Soft Error Detection (SED) Function
Product Bulletin PB1384 April 2017 Rev 1.0 ECP5 Product Families Update - Errata to Soft Error Detection (SED) Function Product Affected: All ECP5 TM product families (ECP5, ECP5-5G, ECP5 Automotive) are
More informationMultimedia SoC System Solutions
Multimedia SoC System Solutions Presented By Yashu Gosain & Forrest Picket: System Software & SoC Solutions Marketing Girish Malipeddi: IP Subsystems Marketing Agenda Zynq Ultrascale+ MPSoC and Multimedia
More information借助 SDSoC 快速開發複雜的嵌入式應用
借助 SDSoC 快速開發複雜的嵌入式應用 May 2017 What Is C/C++ Development System-level Profiling SoC application-like programming Tools and IP for system-level profiling Specify C/C++ Functions for Acceleration Full System
More informationNVIDIA'S DEEP LEARNING ACCELERATOR MEETS SIFIVE'S FREEDOM PLATFORM. Frans Sijstermans (NVIDIA) & Yunsup Lee (SiFive)
NVIDIA'S DEEP LEARNING ACCELERATOR MEETS SIFIVE'S FREEDOM PLATFORM Frans Sijstermans (NVIDIA) & Yunsup Lee (SiFive) NVDLA NVIDIA DEEP LEARNING ACCELERATOR IP Core for deep learning part of NVIDIA s Xavier
More informationOpenCV on Zynq: Accelerating 4k60 Dense Optical Flow and Stereo Vision. Kamran Khan, Product Manager, Software Acceleration and Libraries July 2017
OpenCV on Zynq: Accelerating 4k60 Dense Optical Flow and Stereo Vision Kamran Khan, Product Manager, Software Acceleration and Libraries July 2017 Agenda Why Zynq SoCs for Traditional Computer Vision Automated
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP -UHD General Description The Digital Blocks -UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect
More informationParallel to MIPI CSI-2 TX Bridge
January 2015 Reference Design RD1183 Introduction The Mobile Industry Processor Interface (MIPI) has become a specification standard for interfacing components in consumer mobile devices. The MIPI Camera
More information4K HEVC Video Processing with GPU Optimization on Jetson TX1
4K HEVC Video Processing with GPU Optimization on Jetson TX1 Tobias Kammacher Matthias Frei Hans Gelke Institute of Embedded Systems / High Performance Multimedia Research Group Zurich University of Applied
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and
More informationESL design with the Agility Compiler for SystemC
ESL design with the Agility Compiler for SystemC SystemC behavioral design & synthesis Steve Chappell & Chris Sullivan Celoxica ESL design portfolio Complete ESL design environment Streaming Video Processing
More informationAL361A-EVB-A1. Multi-channel Video Processor EVB. Datasheet. (HDMI/AHD-to-HDMI) 2017 by AverLogic Technologies, Corp. Version 1.0
AL361A-EVB-A1 Multi-channel Video Processor EVB (HDMI/AHD-to-HDMI) Datasheet Version 1.0 INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED
More informationSmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User s Guide
SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User s Guide SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User's Guide Table of Contents SmartFusion2
More information1:2 and 1:1 MIPI DSI Display Interface Bridge Soft IP User Guide
1:2 and 1:1 MIPI DSI Display Interface Bridge Soft IP FPGA-IPUG-02001 Version 1.2 November 2016 Contents 1. Introduction... 4 1.1. Quick Facts... 4 1.2. Features... 4 1.3. Conventions... 5 1.3.1. Nomenclature...
More informationDG0723 Demo Guide SmartFusion2 Imaging and Video Kit MIPI CSI-2
DG0723 Demo Guide SmartFusion2 Imaging and Video Kit MIPI CSI-2 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100
More informationIoT Sensor Connectivity and Processing with Ultra-Low Power, Small Form-Factor FPGAs
IoT Sensor Connectivity and Processing with Ultra-Low Power, Small Form-Factor FPGAs Applications Run the Gamut from Sensor Buffers, Signal Aggregation to Embedded Camera, Audio and Display Solutions A
More informationMemory Modules User Guide
FPGA-IPUG-02033-1.0 February 2018 Contents 1. Introduction... 4 2. Memory Modules... 4 2.1. Single Port RAM (RAM_DQ) EBR Based... 5 2.2. Pseudo Dual-Port RAM (RAM_DP) EBR Based... 8 3. IP Generation...
More informationDeveloping a Camera Application with i.mx RT Series
NXP Semiconductors Document Number: AN12110 Application Note Rev. 0, 12/2017 Developing a Camera Application with i.mx RT Series 1. Introduction This application note describes how to develop an HD camera
More informationSBC-S32V234 QUICK START GUIDE (QSG)
SBC-S32V234 QUICK START GUIDE (QSG) Getting started instructions and a Guide to all Hardware, Software, Tools and Document resources www.nxp.com/sbc-s32v234 EXTERNAL USE WHAT IS QUICK START GUIDE? We at
More informationLattice Memory Mapped Interface and Lattice Interrupt Interface User Guide
Lattice Memory Mapped Interface and Lattice Interrupt Interface FPGA-UG-02039-1.1 February 2018 Contents 1. Introduction... 4 2. Lattice Memory Mapped Interface (LMMI)... 4 2.1. Signal Definitions... 4
More informationA new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI based on Cadence VP6 Technology
Dr.-Ing Jens Benndorf (DCT) Gregor Schewior (DCT) A new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI based on Cadence VP6 Technology Tensilica Day 2017 16th
More informationMIPI CSI2-to-CMOS Parallel Sensor Bridge
MIPI CSI2-to-CMOS April 2014 Introduction Reference Design RD1146 The majority of image sensors in the consumer market use the MIPI CSI2 interface. The Mobile Industry Processor Interface (MIPI) has become
More informationS2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
More informationAL362B-EVB-A1. AHD-to-HDMI Quad Box Development Kit by AverLogic Technologies, Corp. Version 1.0
AL362B-EVB-A1 AHD-to-HDMI Quad Box Development Kit Version 1.0 INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY AVERLOGIC FOR ITS USE,
More informationice40 UltraPlus 8:1 Mic Aggregation Demo User Guide
FPGA-UG-02035 Version 1.0 October 2017 Contents 1. Introduction... 3 1.1. Demo Design Overview... 3 2. Functional Description... 3 3. Demo Package... 4 4. ice40 UltraPlus MDP and Resources... 4 4.1. Configuring
More informationLesson 6 Intel Galileo and Edison Prototype Development Platforms. Chapter-8 L06: "Internet of Things ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 6 Intel Galileo and Edison Prototype Development Platforms 1 Intel Galileo Gen 2 Boards Based on the Intel Pentium architecture Includes features of single threaded, single core and 400 MHz constant
More informationice40 Ultra Self-Learning IR Remote User s Guide
ice40 Ultra Self-Learning IR Remote User s Guide June 2014 UG74_1.0 Introduction ice40 Ultra Self-Learning IR Remote User s Guide This guide describes how to use the ice40 Ultra Mobile Development Platform
More informationLattice SDI Quad-view
June 2015 Introduction Reference Design RD1211 This document describes a Lattice design solution for HD SDI digital video Quad-view recorder that enables SDI video capture to DDR3 memory and playback with
More informationModel: LT-125 USER MANUAL. A Lattice ECP3 based HD video compression and decompression evaluation platform. AUGUST Page 1
Model: LT-125 USER MANUAL A Lattice ECP3 based HD video compression and decompression evaluation platform. AUGUST 2012 Page 1 TABLE OF CONTENTS Table of Contents... 2 Special handling instructions... 3
More informationDeveloping a simple UVC device based on i.mx RT1050
NXP Semiconductors Document Number: AN12103 Application Note Rev. 0, 12/2017 Developing a simple UVC device based on i.mx RT1050 1. Introduction USB Video Class (UVC) describes the capabilities and characteristics
More informationLCMXO3LF-9400C Simple Hardware Management Demo User Guide
LCMXO3LF-9400C Simple Hardware Management Demo FPGA-UG-02021 Version 1.0 June 2017 Contents 1. Introduction... 4 1.1. Demo Design Overview... 4 1.2. MachXO3-9400 Development Board and Resources... 4 2.
More informationBring Intelligence to the Edge with Intel Movidius Neural Compute Stick
Bring Intelligence to the Edge with Intel Movidius Neural Compute Stick Darren Crews Principal Engineer, Lead System Architect, Intel NTG Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION
More informationP I X E V I A : A I B A S E D, R E A L - T I M E C O M P U T E R V I S I O N S Y S T E M F O R D R O N E S
P I X E V I A : A I B A S E D, R E A L - T I M E C O M P U T E R V I S I O N S Y S T E M F O R D R O N E S Mindaugas Eglinskas, CEO at PIXEVIA www.pixevia.com Origins in R&D projects for Lithuanian MoD.
More informationForza 4 ASCII Game. Demo for the AK-MACHX
Forza 4 ASCII Game Demo for the AK-MACHX02-7000 Contents About this document... 3 Revision history... 3 Contact information... 3 Regarding this document... 3 Copyright information... 3 Forza 4 ASCII Game...
More informationDisplayPort MegaCore. Altera Technology Roadshow 2013
DisplayPort MegaCore Altera Technology Roadshow 2013 Agenda DisplayPort Background Introducing DisplayPort MegaCore 2 DisplayPort Background Display Port: What is it? Next generation video display interface
More informationDesigning with NXP i.mx8m SoC
Designing with NXP i.mx8m SoC Course Description Designing with NXP i.mx8m SoC is a 3 days deep dive training to the latest NXP application processor family. The first part of the course starts by overviewing
More informationSundance Multiprocessor Technology Limited. Capture Demo For Intech Unit / Module Number: C Hong. EVP6472 Intech Demo. Abstract
Sundance Multiprocessor Technology Limited EVP6472 Intech Demo Unit / Module Description: Capture Demo For Intech Unit / Module Number: EVP6472-SMT911 Document Issue Number 1.1 Issue Data: 6th October
More informationMicrotronix Stratix III Broadcast IP Development Kit USER MANUAL REVISION Woodcock St. London, ON Canada N5H 5S1
Microtronix Stratix III Broadcast IP Development Kit USER MANUAL REVISION 1.0 9-1510 Woodcock St. London, ON Canada N5H 5S1 www.microtronix.com Document Revision History This user guide provides basic
More informationLatticeECP3 Digital Front End Demonstration Design User s Guide
LatticeECP3 Digital Front End User s Guide September 2013 UG68_01.0 Introduction LatticeECP3 Digital Front End This document provides technical information and operating instructions for LatticeECP3 Digital
More informationAvnet Zynq Mini Module Plus Embedded Design
Avnet Zynq Mini Module Plus Embedded Design Version 1.0 May 2014 1 Introduction This document describes a Zynq standalone OS embedded design implemented and tested on the Avnet Zynq Mini Module Plus. 2
More informationAdvanced Digital Machine Vision Cameras. GigE/USB3 Application. Quick Start. Application Notes. Rugged Machine Vision. Rev D
Rugged Machine Vision Advanced Digital Machine Vision Cameras GigE/USB3 Application Quick Start Application Notes Rugged Machine Vision Advanced Digital Machine Vision Cameras INTRODUCTION This document
More information4.1 Design Concept Demonstration for Altera DE2-115 FPGA Board Demonstration for Cyclone III Development Board...
CONTENTS CHAPTER 1 INTRODUCTION OF THE AHA-HSMC... 1 1.1 Features...1 1.2 About the KIT...2 1.3 Getting Help...3 CHAPTER 2 AHA CARD ARCHITECTURE... 4 2.1 Layout and Components...4 2.2 Block Diagram of
More informationENABLING MOBILE INTERFACE BRIDGING IN ADAS AND INFOTAINMENT APPLICATIONS
ENABLING MOBILE INTERFACE BRIDGING IN ADAS AND INFOTAINMENT APPLICATIONS September 2016 Lattice Semiconductor 111 5 th Ave., Suite 700 Portland, Oregon 97204 USA Telephone: (503) 268-8000 www.latticesemi.com
More informationDPM Demo Kit User s Manual Version: dpm_dk_um_1_0_1.doc
DPM Demo Kit User s Manual Version: 1.0.1 dpm_dk_um_1_0_1.doc 1 INTRODUCTION... 3 2 INSTALLATION... 5 2.1 HARDWARE DELIVERABLES... 5 2.2 SOFTWARE... 5 2.3 CONFIGURATION DATA... 5 2.4 DIRECTORY STRUCTURE...
More informationSC2000 Smart Kit Selection Checklist
SC2000 Smart Kit Selection Checklist Rev 0.3 13 August 2018 1 Copyright 2018 Warranty and Disclaimer The use of the deliverables (e.g. software, application examples, target boards, evaluation boards,
More informationThe BlueNRG-1, BlueNRG-2 BLE OTA (over-the-air) firmware upgrade
Application note The BlueNRG-1, BlueNRG-2 BLE OTA (over-the-air) firmware upgrade Introduction This application note describes the BlueNRG-1, BlueNRG-2 over-the-air (OTA) firmware upgrade procedures running
More informationAL362B-DMB-A0. 4K HDMI Quad DEMO Board. Version 1.1. Mode IN1 IN2 IN3 IN4 Power RS232 IR
AL362B-DMB-A0 4K HDMI Quad DEMO Board Version 1.1 Mode IN1 IN2 IN3 IN4 Power 1 2 3 4 RS232 IR INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED
More informationPrem Arora Microsemi Corporation. Multiple MIPI CSI-2 SM Camera Solution Using FPGAs
Prem Arora Microsemi Corporation Multiple MIPI SM Camera Solution Using FPGAs Agenda History & adoption of MIPI image sensors FPGAs in Imaging/Video applications Applications for multiple MIPI image sensors
More informationB-191 B-191s B-192 B-192S. B-190 Series - Range. 1000x. 600x. 1000x. 600x
B-190 Series - Range B-191 B-191s 1 1 600x Entry level model with monocular head up to total magnification, mechanical stage and exclusive X-LED 2 for unmatchable performance, powerful and uniform illumination.
More informationAL582C-EVB-A0 Evaluation Board
AL582C-EVB-A0 Evaluation Board User Manual Version 1.0 INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY AVERLOGIC FOR ITS USE, OR FOR
More informationAlpha FX Core IP-Enabled Video Wall Controller
SCHEDULE A LIVE DEMO 1.844.891.6090 sales@cinemassive.com Alpha FX Core IP-Enabled Video Wall Controller The Alpha FX Core is a multi-4k, IP-capable video wall controller that delivers extraordinary performance
More informationQuick Start Guide. SABRE Platform for Smart Devices Based on the i.mx 6 Series
Quick Start Guide SABRE Platform for Smart Devices Based on the i.mx 6 Series Quick Start Guide About the SABRE Platform for Smart Devices Based on the i.mx 6 Series The Smart Application Blueprint for
More informationAdvanced Digital Design Using FPGA. Dr. Shahrokh Abadi
Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1 Venue Computer Lab: Tuesdays 10 12 am (Fixed) Computer Lab: Wednesday 10-12 am (Every other odd weeks) Note: Due to some unpredicted problems with
More informationVGA Demo. Forza 4 and Slideshow
VGA Demo Forza 4 and Slideshow VGA Demo - Forza 4 and Slideshow for the AK-MACHX02-7000 Contents About this document... 3 Revision history... 3 Contact information... 3 Regarding this document... 3 Copyright
More informationEfficient Video Processing on Embedded GPU
Efficient Video Processing on Embedded GPU Tobias Kammacher Armin Weiss Matthias Frei Institute of Embedded Systems High Performance Multimedia Research Group Zurich University of Applied Sciences (ZHAW)
More informationIntel Galileo gen 2 Board
Intel Galileo gen 2 Board The Arduino Intel Galileo board is a microcontroller board based on the Intel Quark SoC X1000, a 32- bit Intel Pentium -class system on a chip (SoC). It is the first board based
More informationArduCAM USB Camera SDK
ArduCAM USB Camera SDK User Guide Rev 1.0, April 2017 Table of Contents 1 Introduction... 2 2 USB SDK Library... 2 3 Demo Code... 2 3.1 Thread.cpp... 2 3.2 USBTestDlg.cpp... 2 4 ArduCAM APIs... 2 4.1 Data
More informationSVM-03/03U Utility Software. [SVMCtl] Software Manual. Rev. 8.1
SVM-03/03U Utility Software [SVMCtl] Software Manual Rev. 8.1 NetVision Co., Ltd Revision History NetVision Co., Ltd. Edition Date Detail Charge 1st 2014/06/25 The first edition N. Kashiwagi 2nd 2015/05/12
More informationAcadia II Product Guide. Low-Power, Low-Latency Video Processing for Enhanced Vision in Any Condition
Acadia II Product Guide Low-Power, Low-Latency Video Processing for Enhanced Vision in Any Condition The Acadia II SoC is a state-of-the-art solution for integrated vision processing. Built around advanced
More informationMIPI : Advanced Driver Assistance System
MIPI : Advanced Driver Assistance System application and system development Richard Sproul Charles Qi - Gabriele Zarri (Cadence) esame Conference Sophia Antipolis 05 October 2015 ADAS : some history FORD
More informationAtlys (Xilinx Spartan-6 LX45)
Boards & FPGA Systems and and Robotics how to use them 1 Atlys (Xilinx Spartan-6 LX45) Medium capacity Video in/out (both DVI) Audio AC97 codec 220 US$ (academic) Gbit Ethernet 128Mbyte DDR2 memory USB
More informationFreeBSD and Beaglebone Black, a robotic application.
FreeBSD and Beaglebone Black, a robotic application. Fabio Balzano fabio.balzano@elfarolab.com University of Ottawa, Canada May 17, 2014 The robot System description What is this? it is a ROV - Remote
More informationThe Design of Sobel Edge Extraction System on FPGA
The Design of Sobel Edge Extraction System on FPGA Yu ZHENG 1, * 1 School of software, Beijing University of technology, Beijing 100124, China; Abstract. Edge is a basic feature of an image, the purpose
More informationImplementing Video and Image Processing Designs Using FPGAs. Click to add subtitle
Implementing Video and Image Processing Designs Using FPGAs Click to add subtitle Agenda Key trends in video and image processing Video and Image Processing Suite Model-based design for video processing
More informationFull Linux on FPGA. Sven Gregori
Full Linux on FPGA Sven Gregori Enclustra GmbH FPGA Design Center Founded in 2004 7 engineers Located in the Technopark of Zurich FPGA-Vendor independent Covering all topics
More information4K Video Processing and Streaming Platform on TX1
4K Video Processing and Streaming Platform on TX1 Tobias Kammacher Dr. Matthias Rosenthal Institute of Embedded Systems / High Performance Multimedia Research Group Zurich University of Applied Sciences
More informationUM1853 User manual. STM32CubeF1 Nucleo demonstration firmware. Introduction
User manual STM32CubeF1 Nucleo demonstration firmware Introduction STMCube initiative was originated by STMicroelectronics to ease developers life by reducing development efforts, time and cost. STM32Cube
More informationpcduino V3B XC4350 User Manual
pcduino V3B XC4350 User Manual 1 User Manual Contents Board Overview...2 System Features...3 Single-Board Computer Configuration......3 Pin Assignments...4 Single-Board Computer Setup...6 Required Hardware...6
More informationMicrobee Technology FTM-3SE
Microbee Technology FTM-3SE Freescale Tower System Compatible Field Programmable Gate Array Module TWR-K70 Demo Quick Start Guide The flexibility that programmable logic brings to hardware design has now
More informationThe Information contained herein is subject to change without notice. Revisions may be issued regarding changes and/or additions.
Cobalt MC Gumstix, Inc. shall have no liability of any kind, express or implied, arising out of the use of the Information in this document, including direct, indirect, special or consequential damages.
More informationOverview of the Raspberry Pi Models 3B & 2B
Overview of the Raspberry Pi Models 3B & 2B (Let's look at the hardware!) Rick Commo, K7LOG Max Vaughan, KF7MAX What's really different between the original 2B and the 3B? Parameter Architecture CPU
More information