Computer Architecture ELEC2401 & ELEC3441

Transcription

1 Computer Architecture ELEC241 & ELEC3441 Lecture 4 Sigle Cycle Processor Dr. Hayde Kwok-Hay So Departmet of Electrical ad Electroic Egieerig Overview irst implemetatio the RISC-V ISA i this course More variatios to come Sigle cycle processor: Each istructio takes 1 cycle to complete Idealized memory Istataeous read Sigle cycle write Implemets base RV32 2 ull RISCV1Stage path (HW1) Hare Elemets 13 br/jmp jalr pc_sel val +4 Istructio Mem +4 Ist ir[31], ir[7], ir[3:25], ir[11:8]] ir[31:2] ir[24:2] ir[19:15] Jump argge BrJmp argge Bype Sig ed Iype Sig ed ile Brach CodGe br_eq? br_lt? br_ltu? cotrol status registers wb_sel ir[11:7] rf_ ile e Combiatioal circuits Mux, Decoder,,... A A 1 A -1. Sel Mux lg() O Sychroous state elemets lipflop, ister, ister file, SRAM, DRAM A lg() Decoder. O O 1 O -1 A B OpSelect -, Sub,... - Ad, Or, or, Not,... - G, L, EQ, Zero,... Result Comp? Decoder Sigals Op1Sel Aluu ata mem_rw mem_val Mem cpr_e tohost testrig_tohost E Clk D Q Clk E D Q Execute Stage 3 Edge-triggered: is sampled at the risig edge 4

2 ister E Clk D Q register... D 1 A -bit register ca be costructed by combiig Ds i parallel Each D resposible for read/write of 1 bit of the iput Shared cotrol sigal: Clock, reset, eable, Q 1 D 2 Q D -1 Q -1 D<-1:> D e Q Q<-1:> ister ile Reads are combiatioal =regfile(ra) i the same cycle Writes take place at risig the clock edge Write oly take place if WE=1 at clock edge Read ess (ra) ad write ess () choose which register to read/write RISCV eeds a register file with 2 read ports ad 1 write port What happe i these cases? =! = 1! Readr1 Readr2 Writer Write Clock WE ister file 2R+1W 1 2 Read1 Read2 5 6 ister ile Implemetatio reg A Simple Model WriteEable Clock reg 1 reg 31 ress Write MAGIC RAM 32 Read 2R + 1W, 32 registers, each 32 bits wide Decoder select 1 out of 32 register depedig o,, O writes: Oly 1 of the 32 register has WE=1 O reads: Oly 1 of the 32 register may output to {1,2} bus he same register may output to both 1 ad 2 bus (e.g. = ) Reads ad writes are alys completed i oe cycle a Read ca be doe ay Vme (i.e. combiavoal) a Write is performed at the risig clock edge if it is eabled the write ess ad must be stable at the clock edge Later i the course will preset a more realis:c model of memory 7 8

3 Istructio Executio ExecuVo of a RISC-V istrucvo ivolves: 1. istrucvo fetch 2. decode ad register fetch 3. operavo 4. memory operavo (opvoal) 5. write back to register file (opvoal) + the computavo of the ext istruc:o ess 9 path: - Istructios ist Ist. Ist<19:15> Ist<24:2> Ist <31:25,14:12> WriteE 1 2 Write imig? fuct7 fuct src2 src1 /SL/SLU dest OP src2 src1 AND/OR/OR dest OP src2 src1 SLL/SRL dest OP 1 src2 src1 ENGG3441 SUB/SRA - HS dest OP 1 () fuc () path: -Imm Istructios Coflicts i Mergig path ist Ist. ist<19:15> ist ist<31:2> WriteE 1 2 Sig ist Ist. <19:15> <24:2> <31:2> WriteE 1 2 Sig Itroduce muxes ist<14:12> <31:25,14:12> <14:12> () op imm imm[11:] fuct I-immediate[11:] src I/SLI[U] dest OP-IMM I-immediate[11:] src ANDI/ORI/ORI dest OP-IMM fuct7 fuct3 R-type imm[11:] fuct3 I-type imm[11:5] fuct3 imm[4:] S-type 12

4 Op2 Select If OODE== OP the op2sel = 1 else Copyright , he ets of the Uiversity WriteE of Califoria. All rights reserved <19:15> fuct7 fuct7 <24:2> fuct3 fuct3 R-type R-type imm[11:] imm[11:] fuct3 fuct3 1 I-type I-type imm[11:5] imm[11:5] ist fuct3 fuct3 imm[4:] imm[4:] S-type S-type imm[12 1:5] imm[12 1:5] fuct3 fuct3 2 imm[4:1 11] imm[4:1 11] SB-type SB-type Ist. U-type U-type imm[2 1: :12] imm[2 1: :12] UJ-type UJ-type <31:2> Sig RV32I RV32I Base Base Istructio Istructio Set Set LUI LUI,imm,imm AUI AUI,imm,imm imm[2 1: :12] imm[2 1: :12] JAL JAL,imm,imm imm[11:] imm[11:] JALR JALR,,imm,,imm imm[12 1:5] imm[4:1 11] 1111 BEQ,,imm imm[12 1:5] 1 imm[4:1 11] 1111 BNE,,imm imm[12 1:5] 1 imm[4:1 11] 1111 BL,,imm imm[12 1:5] 11 imm[4:1 11] 1111 BGE,,imm op2sel imm[12 1:5] 11 imm[4:1 11] 1111 BLU,,imm / Imm imm[12 1:5] 111 imm[4:1 11] 1111 BGEU,,imm imm[11:] 11 LB,,imm fuct7 fuct3 R-type imm[11:] 1 11 LH imm[11:] imm[11:] 1 fuct3 11 LW,,immI-type imm[11:5] imm[11:] 1 fuct3 imm[4:] 11 LBU,,imm S-type imm[11:] LHU,,imm imm[11:5] imm[4:] 111 SB,,imm imm[11:5] 1 imm[4:] 111 SH,,imm imm[11:5] 1 imm[4:] 111 SW,,imm imm[11:] 111 I,,imm Determiig imm[11:] 1 fuctios 111 SLI,,imm imm[11:5] imm[11:] 1 11 imm[4:] SW SLIU,,imm,,imm imm[11:] I ORI,,imm,,imm imm[11:] SLI ORI,,imm,,imm imm[11:] ANDI,,imm shamt SLLI,,shamt shamt SRLI,,shamt 1 shamt SRAI,,shamt 1111,, SUB,, SLL,, SL,, SLU,, All basic iteger R-R istructios 1 have 1111 OR = OP,, SRL,, ( 1111 ) SRA,, oly fuct3 ad fuct7 are eeded 11 to determie 1111 eeded OR,, fuctio: AND,, pred succ 1111 ENCE E.g. è, 1èShiftLeft, 1èOR,1èSub, 1111 ENCE.I SCALL Immediate istructios 1 requires the same SBREAK fuctio, but 11 has slightly dieret ecodig RDCYCLE RDIME RDINSRE I is same as, except o eed to check for Sub i fuct7 = OP-IMM ( 111 ) Need to help determie fuctio More cases like these come up later Quick Quiz If OODE== OP the op2sel = 1 else How do you implemet op2sel i hare? OP =? OP =? 1 1 op2sel op2sel How do you implemet this? 14 Istructios path ist Ist. <19:15> <24:2> <31:2> <3,14:12,6:> WriteE 1 2 Sig Copyright , he ets of the Uiversity of Califoria. All rights reserved. 51 / Imm fuct7 fuct3 R-type imm[11:] fuct3 I-type imm[11:5] fuct3 imm[4:] S-type imm[12 1:5] fuct3 imm[4:1 11] SB-type U-type imm[2 1: :12] UJ-type =? 16

5 I Load Istructios imm[11:] f3 oset[11:] base width dest LOAD Load: (dest) ß M[(base) + oset] Use for ess calculatio Mux to select for regfile: mem or Store Istructios S imm[11:5] f3 imm[4:] oset[11:5] src base width oset[4:] SORE Also use for ess calculatio No eed to write back to regfile Need to tell memory it is a write è Set to 1 Store: M[(base) + oset] ß (src) ist Ist. base oset WriteE 1 2 Sig ata / Mem ist Ist. base oset WriteE 1 2 Sig ata / Mem RISC-V Coditioal Braches imm[12] SB imm[1:5] fuct3 imm[4:1] oset[12,1:5] src2 src1 BEQ/BNE oset[11,4:] BL[U] BGE[U} imm[11] BRANCH Coditioal Braches (BEQ/BNE/BL/BGE/BLU/BGEU) Sel br WrE if ( BR_OP ) the jump to + brach_imm Requires: 1. Logic to compare register values ( ad ) 2. path to calculate brach target ess relative to Curret implemetatio: dedicated logic for both 1 ad 2 Dedicated compariso logic (=, <, [, ]) Dedicated adder for jump target calculatio May use for (2) above Performace tradeo ist Ist. 1 2 Brach Imm Br Logic ata 19 2

6 RISC-V Ucoditioal JAL Sel brjmp imm[2] UB Imm[11] imm[1:1] imm[19:12] oset[2:1] dest JAL jump to + j_imm; ß +4 WrE JALR I imm[11:] f3 oset[11:] base dest JALR Sel WrE brjmp jmpreg jump to imm + (); ß +4 ist Ist. 1 2 Brach Imm Jump Imm Br Logic ata ist Ist. oset 1 2 Sig Br Logic ata Hawired is pure Combiatioal Logic op code combiavoal logic Aluuc WriteE Sel Decodig istructio determies the settig of various muxes ad fuctio Simple decodig helps to make faster hare Hawired able (Excerpt) Istructio Aluuc WriteE Sel SUB I SLL LW SW BEQ JAL JALR RS2 RS2 IMI RS2 IMI IMS IMB IMJ IMI SUB SLL MEM :, {I,B,J}-type immediate IM{I, B, J} Aluuc:, Sub, Shift, OR, etc : what values to write to N N N /BA JA JRA 23 24

7 Sigle-Cycle Hawired We will assume clock period is suicietly log for all of the followig steps to be completed : 1. Istructio fetch 2. Decode ad register fetch 3. operatio 4. fetch if required 5. ister write-back setup time 13 ull RISCV1Stage path (HW1) br/jmp jalr pc_sel val +4 Istructio Mem +4 Ist ir[31], ir[7], ir[3:25], ir[11:8]] ir[31:2] ir[24:2] ir[19:15] Jump argge BrJmp argge Bype Sig ed Iype Sig ed ile Brach CodGe br_eq? br_lt? br_ltu? cotrol status registers wb_sel ir[11:7] rf_ ile e t C > t Ietch + t Retch + t + t DMem + t RWB At the risig edge of the followig clock, the, register file ad memory are updated Decoder Sigals Op1Sel Aluu ata mem_rw mem_val Mem cpr_e tohost testrig_tohost Execute Stage Ackowledgemets hese slides cotai material developed ad copyright by: Arvid (MI) Krste Asaovic (MI/UCB) Joel Emer (Itel/MI) James Hoe (CMU) Joh Kubiatowicz (UCB) David Patterso (UCB) MI material derived from course UCB material derived from course CS152, CS252 27