Computer Organization. Submitted By: Dalvir Hooda

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1 Computer Organization Submitted By: Dalvir Hooda

2 3 Fundamental Components of Computer The CPU (ALU, Control Unit, Registers) The Memory Subsystem (Stored Data) The I/O subsystem (I/O devices) CPU Address Bus Data Bus Control Bus 2 I/O Device Subsystem Memory Subsystem

3 Each of these Components are connected through Buses. BUS - Physically a set of wires. The components of the Computer are connected to these buses. Address Bus Data Bus Control Bus 3

4 Address Bus Used to specify the address of the memory location to access. Each I/O devices has a unique address. (monitor, mouse, cd- rom) CPU reads data or instructions from other locations by specifying the address of its location. CPU always outputs to the address bus and never reads from it. 4

5 Data Bus Actual data is transferred via the data bus. When the cpu sends an address to memory, the memory will send data via the data bus in return to the cpu. 5

6 Control Bus Collection of individual control signals. Whether the cpu will read or write data. CPU is accessing memory or an I/O device Memory or I/O is ready to transfer data 6

7 I/O Bus or Local Bus In today s computers the the I/O controller will have an extra bus called the I/O bus. The I/O bus will be used to access all other I/O devices connected to the system. Example: PCI bus 7

8 Instruction Cycles Procedure the CPU goes through to process an instruction. 1. Fetch - get instruction 2. Decode - interperate the instruction 3. Execute - run the instruction. 8

9 CPU organization CPU controls the Computer The CPU will fetch, decode and execute instructions. The CPU has three internal sections: register section, ALU and Control Unit 9

10 Register Section Includes collection of registers and a bus. Processor s instruction set architecture are found in this section. Non accessible registers by the programmer. These are to be used for registers to latch the address being accessed and a temp storage register. 10

11 Arithmetic/Logic Unit (ALU) Performs most Arithmetic and logical operations. Retrieves and stores its information with the register section of the CPU. 11

12 MEMORY ORGANIZATION 12 Memory Hierarchy Main Memory Auxiliary Memory Associative Memory Cache Memory Virtual Memory Memory Management Hardware`

Memory Main memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each

13 Memory Main memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 16, 24, 32 or as many as 64 bits. A large word length improves system performance, though may be less efficient on occasions when the full word length is not used 13

14 Memory Hierarchy MEMORY HIERARCHY Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system Auxiliary memory Magnetic tapes I/O processor Main memory CPU Cache memory Magnetic disks Register Cache Main Memory Magnetic Disk Magnetic Tape 14

15 Memory Subsystem 2 Types of Memory: ROM : Read Only Memory Program that is loaded into memory and cannot be changed also retains its data even without power. RAM : Random Access Memory Also called read/write memory. This type of memory can have a program loaded and then reloaded. It also loses its data with no power. 15

16 Different ROM Chips Masked ROM : ROM that is programmed with data when fabricated. Data will not change once installed. Hardwired. Programmable ROM (PROM) : Capable of being programmed by the user with a ROM programmer. Not hardwired. Erasable PROM (EPROM) : Much like the PROM this EPROM can be programmed and then erased by light. EEPROM : Another form of EPROM but is reprogammable electrically. 16

17 Different RAM Chips Dynamic RAM (DRAM) : Leaky capacitors. Caps are charged and slowly leak until they are refreshed to there original data locations. Ex. Computer RAM Static RAM (SRAM) : Much like a register. The contents stay valid and does not have to be refreshed. SRAM is faster than DRAM but cost more Ex. Cache Each RAM chip has 2^n * m. n address inputs and m bidirectional data pins 17

18 The operation of cache memory 1. Cache fetches data from next to current addresses in main memory 2. CPU checks to see whether the next instruction it requires is in cache Cache Main CPU Memory Memory (SRAM) (DRAM) 4. If not, the CPU has to fetch next instruction from main memory - a much slower process If it is, then the instruction is fetched from the cache a very fast position = Bus connections

19 Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack 19

20 Immediate Addressing Operand is part of instruction Operand = address field e.g. ADD 5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range 20

21 Immediate Addressing Diagram Instruction Opcode 21 Operand

22 Direct Addressing Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Limited address space 22

23 Direct Addressing Diagram Instruction Opcode Address A Memory Operand 23

24 Direct Addressing Diagram Instruction Opcode Address A Memory Operand 24

25 Indirect Addressing (1) Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator 25

26 Indirect Addressing (2) Large address space 2n where n = word length May be nested, multilevel, cascaded e.g. EA = (((A))) Draw the diagram yourself Multiple memory accesses to find operand Hence slower 26

27 Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand 27

28 Register Addressing (1) Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed Shorter instructions Faster instruction fetch 28

29 Register Addressing (2) No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing N.B. C programming register int a; c.f. Direct addressing 29

30 Register Addressing Diagram Instruction Opcode Register Address R Registers Operand 30

31 Register Indirect Addressing C.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory access than indirect addressing 31

32 Register Indirect Addressing Diagram Instruction Opcode Register Address R Memory Registers Pointer to Operand 32 Operand

33 Displacement Addressing EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa 33

34 Displacement Addressing Diagram Instruction Opcode Register R Address A Memory Registers Pointer to Operand 34 + Operand

35 Relative Addressing A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage 35

36 Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86 36

37 Indexed Addressing A = base R = displacement EA = A + (R) Good for accessing arrays EA = A + (R) R++ 37

38 Stack Addressing Operand is (implicitly) on top of stack e.g. ADD and add 38 Pop top two items from stack

39 Input-Output Organization 11-1 Peripheral Devices I/O Subsystem Provides an efficient mode of communication between the central system and the outside environment Peripheral (or I/O Device) Input or Output devices attached to the computer 11-2 Input-Output Interface 1) A conversion of signal values may be required 39

40 2) A synchronization mechanism may be needed The data transfer rate of peripherals is usually slower than the transfer rate of the CPU 3) Data codes and formats in peripherals differ from the word format in the CPU and Memory 4) The operating modes of peripherals are different from each other Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU Interface Special hardware components between the CPU and peripherals Supervise and Synchronize all input and output transfers I/O bus Data Processor Address Control 40 Interface Interface Interface Interface Keyboard and display terminal Printer Magnetic disk Magnetic tape

41 Transfer Synchronous Data Transfer All data transfers occur simultaneously during the occurrence of a clock pulse Registers in the interface share a common clock with CPU registers Asynchronous Data Transfer Internal timing in each unit (CPU and Interface) is independent Each unit uses its own private clock for internal registers 41

42 Data bus Data bus Source unit Strobe Destination unit Source unit Strobe (a) Block diagram (a) Block diagram Valid data Data Strobe Data Strobe Valid data (b) Timing diagram (b) Timing diagram Fig Sourceinitiated strobe 42 Fig Destinationinitiated strobe Destination unit

43 Handshake : Data bus Source unit Data bus Data valid Destination unit Data valid Source unit Data accepted Ready for data (a) Block diagram (a) Block diagram Destination unit Valid data Data Ready for data Data valid Data valid Data accepted Data bus (b) Timing diagram Source unit Place data on bus Enable data valid. Valid data (b) Timing diagram Destination unit Source unit Destination unit Accept data from bus Enable data accepted Ready to accept data. Enable ready for data Place data on bus Enable data valid. Disable data valid Invalidate data on bus Disable data accepted Ready to accept data (initial state) (c) Sequence of events Fig Sourceinitiated handshake 43 Disable data valid Invalidate data on bus (initial state) Accept data from bus Disable reday for data (c) Sequence of events Fig Destinationinitiated handshake

44 11-4 Modes of Transfer Read status register Data transfer to and from peripherals 1) Programmed I/O 2) Interrupt-initiated I/O 3) Direct Memory Access (DMA) 4) I/O Processor (IOP) Interrupt-initiated I/O 1) Non-vectored : fixed branch address 2) Vectored : interrupt source supplies the branch address (interrupt vector) 44 Check flag bit =0 Flag =1 Read data register Transfer data to memory Operation complete? yes Continue with program no

45 Polling Identify the highest-priority source by software means One common branch address is used for all interrupts Program polls the interrupt sources in sequence The highest-priority source is tested first Polling priority interrupt If there are many interrupt sources, the time required to poll them can exceed the time available to service the I/O device 따라서 Hardware priority interrupt Daisy-Chaining : Processor data bus VAD 1 1 Device 1 PI PO VAD 2 1 Device 2 PI PO VAD 3 0 Device 3 PI PO Interrupt request To next Device INT CPU Interrupt acknowledge 45 INTACK

46 VAD INTACK PI INT Priority in Enable Vector address One stage of the daisy-chain priority arrangement : Fig Interrupt request from device S Q Priority out RF PO R PI RF PO Enable Open-collector inverter Invalid : interrupt request,interrupt but no request acknowledge to CPU No interrupt request : Pass to other device (other device requested interrupt ) No interrupt request Interrupt request 46 Delay

47 Direct Memory Access (DMA) DMA DMA controller takes over the buses to manage the transfer directly between the I/O device and memory BR BR Bus request DMA Controller BG Address bus ABUS Data bus CPU RD Read WR Write BG Bus grant 47 DBUS High-impedance (disable) when BG is enabled

48 1) Burst transfer : 2) Cycle stealing transfer DMA Controller ( Intel 8237 DMAC ) DMA Initialization Process 1) Set Address register : o memory address for read/write 2) Set Word count register : o the number of words to transfer 3) Set transfer mode : 4) DMA transfer start : 5) EOT (End of Transfer) : Address bus Address bus buffers Data bus buffers Data bus DMA select CS Register select RS Internal bus Transfer Modes Read RD Write WR Bus request BR Bus grant BG Interrupt Interrupt Address register Word count register Control logic Control register DMA request DMA Acknowledge 48 to I/O device

49 DMA Transfer (I/O to Memory) 1) I/O Device sends a DMA request Interrupt 2) DMAC activates the BR line BG 3) CPU responds with BG line BR 4) DMAC sends a DMA acknowledge to the I/O device 5) I/O device puts a word in the data bus (for memory write) 6) DMAC write a data to the address specified by Address register 7) Decrement Word count register 8) Word count 9) Word count register RD WR Address Data RD WR Address Data Read control Write control Data bus Address bus Address select RD WR Address DS RS BR BG Interrupt 49 Random access memory (RAM) CPU Data DMA acknowledge Direct memory access (DAM) controller I/O Peripheral device DMA request

50 Input-Output Processor (IOP) IOP Communicate directly with all I/O devices Fetch and execute its own instruction IOP instructions are specifically designed to facilitate I/O transfer DMAC must be set up entirely by the CPU Designed to handle the details of I/O processing Memory unit Memory bus Central Processing unit (CPU) Peripheral devices PD Input-output processor (IOP) 50 PD PD I/O bus PD

51 CPU - IOP Communication Memory units acts as a message center : each processor leaves information for the other CPU operations Send instruction to test IOP path If status OK., send start I/O instruction to IOP CPU continues with another program IOP operations Transfer status word to memory location Access memory for IOP program Conduct I/O transfer using DMA ; prepare status report I/O transfer completed interrupt CPU Request IOP status Transfer status word to memory location Check status word for correct transfer Continue 51

52 Input/output Devices Input/output devices are required for users to communicate with the computer. In simple terms, input devices bring information INTO the computer and output devices bring information OUT of a computer system. These input/output devices are also known as peripherals. 52

53 Input Devices are: Keyboard Mouse Joystick Scanner Light Pen Touch Screen 53

54 Output devices are: Printers Plotters Monitor LCD 54

55 Intel 8086/8088 Microprocessors Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible computers (8086 introduced in 1978, first IBM-PC released in 1981) All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8 At Power Up and Reset time, Pentiums, Athlons etc all look like 8086 processors 55

56 Intel 8086/8088 Microprocessors Intel 8086 is a 16b microprocessor: 16b data registers, 16b ALU Width of external data bus: 8086: 16b 8088: 8b Width of external address bus: 16b+4b=20b Some techniques to optimise the CPU performance when it s executing programs Segment: Offset memory model Little-Endian Data Format 56

57 8086/8088 Original IBM PC used 8088 microprocessor 8088 is similar to the 8086, but it has an external 8b data bus & only 4B-deep queue For cost reduction reasons We can consider 8086 and 8088 together PC clones often used 8086 for better performance 8-bit bus reduces performance, but meant cheaper computers 57

58 8086/8088 Functional Units Bus Interface Unit(BIU) Fetches Opcodes, Reads Operands, Writes Data Execution Unit (EU) 8086/8088 MPU 58

59 8086/ /8088 consists of two internal units The execution unit (EU) - executes the instructions The bus interface unit (BIU) - fetches instructions, reads operands and writes results The 8086 has a 6B prefetch queue The 8088 has a 4B prefetch queue 59

60 8086/8088 Internal Organisation EU BIU Addres s Bus 20 bits AH AL BH BL CH CL DH DL SUMMATION Data Bus CS DS SP SS BP ES DI IO BI Bus Control Internal Com m unications Regis ters 8088 Bus Tem porary Regis ters Ins truction Queue ALU EU Control Flags

61 BIU Elements Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction The memory interface is slower than the processor execution time so this speeds up overall performance Segment Registers: CS, DS, SS and ES are 16b registers Used with the 16b Base registers to generate the 20b address Allow the 8086/8088 to address 1MB of memory Changed under program control to point to different segments as a program executes Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register 61

62 8086/ bit Addresses CS 16-bit Segnment Base Address IP 16-bit Offset Address 20-bit Physical Address

63 BIU Elements Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction The memory interface is slower than the processor execution time so this speeds up overall performance Segment Registers: CS, DS, SS and ES are 16b registers Used with the 16b Base registers to generate the 20b address Allow the 8086/8088 to address 1MB of memory Changed under program control to point to different segments as a program executes Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register 63

64 MAXIMUM MODE GND 1 Vcc AD14 AD15 AD13 A16,S3 AD12 A17,S4 AD11 A18,S5 AD10 A19,S6 AD9 /BHE,S7 AD8 MN,/MX AD7 /RD AD6 /RQ,/GT0 HOLD /RQ,/GT1 HLDA AD4 /LOCK /WR AD3 /S2 IO/M AD2 /S1 DT/R AD1 /S0 /DEN AD0 QS0 ALE NMI QS1 /INTA 8086 AD5 INTR /TEST CLK READY GND MINIMUM MODE RESET

65 8086/8088 Summary First Generation (introduced June 1978) One of the first 16b processors on the market 16b internal registers 16/8b external data bus 20b address bus (1MB addressable) Used in 1st generation IBM PCs (1981) 65

66 Multiprocessor Systems Continuous need for faster computers shared memory model message passing multiprocessor wide area distributed system

67 Multiprocessors Definition: A computer system in which two or more CPUs share full access to a common RAM

68 Multiprocessor Hardware (1) Bus-based multiprocessors 68

69 Multiprocessor Hardware (2) UMA Multiprocessor using a crossbar switch

70 Multiprocessor Hardware (3) UMA multiprocessors using multistage switching networks can be built from 2x2 switches (a) 2x2 switch (b) Message format

71 Multiprocessor Hardware (4) Omega Switching Network

72 Multiprocessor Hardware (5) NUMA Multiprocessor Characteristics 1. Single address space visible to all CPUs 2. Access to remote memory via commands - 3. LOAD STORE Access to remote memory slower than to local

73 Multiprocessor Hardware (6) (a) 256-node directory based multiprocessor (b) Fields of 32-bit memory address (c) Directory at node 36

74 Multiprocessor OS Types (1) Bus Each CPU has its own operating system

75 Multiprocessor OS Types (2) Bus Master-Slave multiprocessors

76 Multiprocessor OS Types (3) Bus Symmetric Multiprocessors SMP multiprocessor model

77 Multiprocessor Synchronization (1) TSL instruction can fail if bus already locked

78 Multiprocessor Synchronization (2) Multiple locks used to avoid cache thrashing

79 Multiprocessor Synchronization (3) Spinning versus Switching In some cases CPU must wait waits to acquire ready list In other cases a choice exists spinning wastes CPU cycles switching uses up CPU cycles also possible to make separate decision each time locked mutex encountered

80 Multiprocessor Scheduling (1) Timesharing note use of single data structure for scheduling

81 Multiprocessor Scheduling (2) Space sharing multiple threads at same time across multiple CPUs

82 Multiprocessor Scheduling (3) Problem with communication between two threads both belong to process A both running out of phase

83 Multiprocessor Scheduling (4) Solution: Gang Scheduling Groups of related threads scheduled as a unit (a gang) All members of gang run simultaneously 3. on different timeshared CPUs All gang members start and end time slices together

84 Multiprocessor Scheduling (5) Gang Scheduling

85 Multicomputers Definition: Tightly-coupled CPUs that do not share memory Also known as cluster computers clusters of workstations (COWs)

86 Multicomputer Hardware (1) Interconnection topologies (a) single switch (b) ring (c) grid (d) double torus (e) cube (f) hypercube

87 Multicomputer Hardware (2) Switching scheme store-and-forward packet switching

88 Multicomputer Hardware (3) Network interface boards in a multicomputer

INPUT-OUTPUT ORGANIZATION

INPUT-OUTPUT ORGANIZATION Peripheral Devices: The Input / output organization of computer depends upon the size of computer and the peripherals connected to it. The I/O Subsystem of the computer, provides